Datasheet

AD9734/AD9735/AD9736
Rev. A | Page 6 of 72
DIGITAL SPECIFICATIONS
AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, maximum sample rate, I
FS
= 20 mA, 1× mode, 25 Ω, 1% balanced load,
unless otherwise noted. LVDS drivers and receivers are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit
LVDS DATA INPUT
(DB[13:0]+, DB[13:0]−) DB+ = V
IA
, DB− = V
IB
Input Voltage Range, V
IA
or V
IB
825 1575 mV
Input Differential Threshold, V
IDTH
−100 +100 mV
Input Differential Hysteresis, V
IDTHH
− V
IDTHL
20 mV
Receiver Differential Input Impedance, R
IN
80 120 Ω
LVDS Input Rate 1200 MSPS
LVDS Minimum Data Valid Period (t
MDE
) 344 ps
LVDS CLOCK INPUT
(DATACLK_IN+, DATACLK_IN−) DATACLK_IN+ = V
IA
, DATACLK_IN− = V
IB
Input Voltage Range, V
IA
or V
IB
825 1575 mV
Input Differential Threshold,
1
V
IDTH
−100 +100 mV
Input Differential Hysteresis, V
IDTHH
− V
IDTHL
20 mV
Receiver Differential Input Impedance, R
IN
80 120 Ω
Maximum Clock Rate 600 MHz
LVDS CLOCK OUTPUT
(DATACLK_OUT+, DATACLK_ OUT−) DATACLK_OUT+ = V
oa
, DATACLK_OUT− = V
ob
100 Ω Termination
Output Voltage High, V
OA
or V
OB
1375 mV
Output Voltage Low, V
OA
or V
OB
1025 mV
Output Differential Voltage, |V
OD
| 150 200 250 mV
Output Offset Voltage, V
OS
1150 1250 mV
Output Impedance, Single-Ended, R
O
80 100 120 Ω
R
O
Mismatch Between A and B, ∆R
O
10 %
Change in |V
OD
| Between 0 and 1, |∆V
OD
|
25 mV
Change in V
OS
Between 0 and 1, ∆V
OS
25 mV
Output Current—Driver Shorted to Ground, I
SA
, I
SB
20 mA
Output Current—Drivers Shorted Together, I
SAB
4 mA
Power-Off Output Leakage, |I
XA
|, |I
XB
| 10 mA
Maximum Clock Rate 600 MHz
DAC CLOCK INPUT (CLK+, CLK−)
Input Voltage Range, CLK− or CLK+ 0 800
Differential Peak-to-Peak Voltage 400 800 1600 mV
Common-Mode Voltage 300 400 500 mV
Maximum Clock Rate 1200 MHz
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (f
SCLK
, 1/t
SCLK
) 20 MHz
Minimum Pulse Width High, t
PWH
20 ns
Minimum Pulse Width Low, t
PWL
20 ns
Minimum SDIO and CSB to SCLK Setup, t
DS
10 ns
Minimum SCLK to SDIO Hold, t
DH
5 ns
Maximum SCLK to Valid SDIO and SDO, t
DV
20 ns
Minimum SCLK to Invalid SDIO and SDO, t
DNV
5 ns