Datasheet

AD9734/AD9735/AD9736
Rev. A | Page 56 of 72
POWER SUPPLY SEQUENCING
The 1.8 V supplies should be enabled prior to enabling the 3.3 V supplies. Do not enable the 3.3 V supplies when the
1.8 V supplies are off.
04862-101
LVDS
RX
DATACLK_IN
DATACLK_IN DOMAIN DACCLK DOMAIN
DB<13:0>
PATH A
PATH B
DATACLK_OUT
D1A
DAC_DATA
DAC_OUTPUT
D1
D2
D2A
 SD<3:0>
SAMPLE DELAY
DACCLK
FF
FF
÷ 2
CLK
RX
FF
FF
SD<3:0>
SAMPLE DELAY
DATA SAMPLING
SIGNAL
DAC SAMPLING
SIGNAL
COMMON SYSTEM CLOCK
DELAYS THROUGH PATH A AND B WILL TRACK,
THUS REDUCING TIMING UNCERTAINTY IN THE SYSTEM
LVDS
RX
LVDS
TX
DAC
CORE
Figure 103. Simplified Internal Clock Routing