Datasheet

AD9734/AD9735/AD9736
Rev. A | Page 51 of 72
DAC OUTPUT DISTORTION SOURCES
The second harmonic is mostly due to an imbalance in the
output load. The dc transfer characteristic of the DAC is capable
of second harmonic distortion of at least −75 dBc. Output load
imbalance or digital data noise coupling onto DACCLK causes
additional second harmonic distortion.
The DAC architecture inherently generates third harmonics, the
levels of which depend on the output frequency and amplitude
generated. If any output signal is rectified and coupled back
onto the DAC clock, it can generate additional third-harmonic
energy.
The distortion components should be identical in amplitude
and phase at both AD973x outputs. Even though each single-
ended output includes a large amount of second-harmonic
energy, a careful differential-to-single-ended conversion can
remove most of it. Optimum performance at high intermediate
frequency (IF) output is obtained with the output circuit shown
in
Figure 93.
This is the configuration implemented on the evaluation board
(
Figure 107). The 20 Ω series resistors allow the DAC to drive a
less reactive load, which improves distortion. Further improvement
is realized by adding the Balun T3 to help provide an equal load
to both DAC outputs.
04862-091
IOUTA
IOUTB
J2, 50Ω OUTPUT
AVSS
R17
20Ω
156
5
1
3443
R19
20Ω
T3
T1AVSS
R8
50Ω
R6
50Ω
Figure 93. IF Signal Output Circuit
Because T1 has a differential input, but a single-ended output,
Pin 4 of T1 has a higher capacitance to ground due to parasitics
to Pin 3. T1 Pin 6 has lower parasitic capacitance to ground
because it drives 50 Ω at Pin 1. This presents an unbalanced
load to the DAC output, so T3 is added to improve the load
balancing. Refer to
Figure 107 for the transformer part numbers.