Datasheet

AD9734/AD9735/AD9736
Rev. A | Page 44 of 72
DIGITAL BUILT-IN SELF TEST (BIST)
OVERVIEW
The AD973x includes an internal signature generator that
processes incoming data to create unique signatures. These
signatures are read back from the SPI port, allowing verification
of correct data transfer into the AD973x. BIST vectors provided
on the AD973x-EB evaluation board CD check the full width
data input or individual bits for PCB debug, utilizing the
procedure in the
AD973X BIST Procedure section. Alterna-
tively, any vector can be used provided the expected signature is
calculated in advance.
The MATLAB® routine, in the
Generating Expected Signatures
section, calculates the expected signature. BIST verifies correct
data transfer because not all errors are always evident on a
spectrum analyzer. There are four BIST signature generators
that can be read back using Reg. 18 to Reg. 21, based on the
setting of the BIST selection bits (Reg. 17, Bits 7:6), as shown in
Table 24. The BIST signature returned from the AD973x
depends on the digital input during the test. Because the filters
in the DAC have memory, it is important to put the correct idle
value on the DATA input to flush the memory prior to reading
the BIST signature.
Placing the idle value on the data input also allows the BIST to
be set up while the DAC clock is running. The idle value should
be all 0s in unsigned mode (0x0000) and all 0s except for the
MSB in twos complement mode (0x2000).
The BIST consists of two stages; the first stage is after the LVDS
receiver and the second stage is after the FIFO. The first BIST
stage verifies correct sampling of the data from the LVDS bus
while the second BIST stage verifies correct synchronization
between the DAC_CLK domain and the DATACLK_IN
domain. The BIST vector is generated using 32-bit LFSR
signature logic. Because the internal architecture is a 2-bus
parallel system, there are two 32-bit LFSR signature logic blocks
on both the LVDS and SYNC blocks.
Figure 84 shows where the
LVDS and SYNC phases are located.
Table 24. BIST Selection Bits
Bit SEL<1> SEL<0>
LVDS Phase 1 0 0
LVDS Phase 2 0 1
SYNC Phase 1 1 0
SYNC Phase 2 1 1
LVDS
RX
DB<13:0>
DATACLK_IN
SYNC LOGIC
FIFO 2x
D1
D
2
DAC
LVDS
BIST
PH1
(RISE)
LVDS
BIST
PH2
(FALL)
SYNC
BIST
PH1
(RISE)
SYNC
BIST
PH2
(FALL)
SPI PORT
04862-082
Figure 84. Block Diagram Showing LVDS and SYNC Phase 1 and SYNC Phase 2