Datasheet

AD9734/AD9735/AD9736
Rev. A | Page 43 of 72
D
INTERNAL DELAY
DACCLK
DATACLK_OU
T
DATACLK_IN
DATA_IN
A
A
B
B
01
2 3456701 234
5
670
456701234 1 2345670
C
C
D
D
E
E
F
F
G
G
H
H
I
I
J
J
K
K
L
L
M
A
B
C D E F G H IJKLM
M
N
N
I
A
O
O
Q
P
P
QR
DSS1
DSS2
D2
WRITE_PTR1
SAFE ZONE
DATA 'A' CAN BE
SAFELY READ FROM
THE FIFO IN THE
SAFE ZONE. IN THE
ERROR ZONE, THE
POINTERS MAY
BRIEFLY OVERLAP
DUE TO CLOCK JITTER
OR NOISE.
FIFOSTAT IS SET
EQUAL TO THE
WRITE POINTER
EACH TIME THE
READ POINTER
CHANGES FROM
7 TO 0.
ERROR ZONE
M0
M1 B
C
E
F
G
4
44
H
J
M2
M3
M4
M5
M6
M7
READ_PTR1
FIFOSTAT
DAC_DATA
D1
EXTERNAL DELAY
SAMPLE_HOLD
SAMPLE_SETUP
SAMPLE_DELAY
04862-081
Figure 83. Sync Logic Timing Diagram