Datasheet

AD9734/AD9735/AD9736
Rev. A | Page 39 of 72
INTERPOLATION FILTER
In 2× mode, the input data is interpolated by a factor of 2 so
that it aligns with the DAC update rate. The interpolation filter
is a hard-coded, 55-tap, symmetric FIR with a 0.001 dB pass-
band flatness and a stop-band attenuation of about 90 dB. The
transition band runs from 20% of f
DAC
to 30% of f
DAC
. The FIR
response is shown in
Figure 75 where the frequency axis is
normalized to f
DAC
. Figure 76 shows the pass-band flatness and
Table 23 shows the 16-bit filter coefficients.
Table 23. FIR Interpolation Filter Coefficients
Coefficient Number Coefficient Number Tap Weight
1 55 −7
2 54 0
3 53 +24
4 52 0
5 51 −62
6 50 0
7 49 +135
8 48 0
9 47 −263
10 46 0
11 45 +471
12 44 0
13 43 −793
14 42 0
15 41 +1273
16 40 0
17 39 −1976
18 38 0
19 37 +3012
20 36 0
21 35 −4603
22 34 0
23 33 +7321
24 32 0
25 31 −13270
26 30 0
27 29 +41505
28 +65535
04862-073
FREQUENCY NORMALIZED TO f
DAC
0.500 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
MAGNITUDE (dB)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Figure 75. Interpolation Filter Response
04862-074
FREQUENCY NORMALIZED TO f
DAC
0.250 0.100.05 0.15 0.20
MAGNITUDE (dB)
0.10
0.06
0.08
0.02
–0.02
–0.06
0.04
0
–0.04
–0.08
–0.10
Figure 76. Interpolation Filter Pass-Band Flatness
DATA INTERFACE CONTROLLERS
Two internal controllers are utilized in the operation of the
AD973x. The first controller helps maintain optimum LVDS
data sampling; the second controller helps maintain optimum
synchronization between the DACCLK and the incoming data.
The LVDS controller is responsible for optimizing the sampling
of the data from the LVDS bus (DB13:0), while the sync
controller resolves timing problems between the DAC_CLK
(CLK+, CLK−) and the DATACLK. A block diagram of these
controllers is shown in
Figure 77.
DATACLK_OUT
DATACLK
DATACLK_IN
FIFO
DAC
LVDS
SAMPLE
LOGIC
CLK
CONTROL
LVDS
CONTROLLER
DB<13:0>
DATA
SOURCE
i.e., FPGA
SYNC
LOGIC
SYNC
CONTROLLER
04862-075
Figure 77. Data Controllers
The controllers are clocked with a divided-down version of the
DAC_CLK. The divide ratio is set utilizing the controller clock
predivider bits (CCD<3:0>) located at Reg. 22, Bits 3:0 to
generate the controller clock as follows:
Controller Clock = DAC_CLK/(2(CCD<3:0> + 4))
Note that the controller clock cannot exceed 10 MHz for correct
operation. Until CCD<3:0> is properly programmed to meet
this requirement, the DAC output may not be stable. This
means the FIFO cannot be enabled in PIN_MODE unless the
DACCLK is less than 160 MHz.