Datasheet

AD9734/AD9735/AD9736
Rev. A | Page 34 of 72
CONTROLLER CLOCK PREDIVIDER (CCLK_DIV) READING REGISTER (REG. 22)
ADR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0x16 CCLK_DIV RESERVED RESERVED RESERVED RESERVED CCD<3> CCD<2> CCD<1> CCD<0>
Table 18. Controller Clock Predivider Register Bit Descriptions
Bit Name Read/Write Description
CCD<3:0> WRITE
0x0, controller clock = DACCLK/16.
0x1, controller clock = DACCLK/32.
0x2, controller clock = DACCLK/64 …
0xF, controller clock = DACCLK/524288.
NOTE: The 100 MHz to 1.2 GHz DACCLK must be divided to less than 10 MHz for correct operation. CCD<3:0>
must be programmed to divide the DACCLK so that this relationship is not violated. Controller clock =
DACCLK/(2 ^ ( CCD<3:0> + 4 )).