Datasheet

AD9726
Rev. B | Page 7 of 24
0
4540-101
CLK+/CLK–
IOUTA OR IOUTB
t
PIPE-BYPASS
+ t
PD-BYPASS
DB0 TO DB15
Figure 5. Data Synchronization Bypass Pipeline Delay
CSB
SCLK
S
DIO (SD0)
t
CPWH
t
DSU
t
DH
t
CPWL
04540-004
SCLK SET-UP TIME
SDIO SET-UP TIME SDIO HOLD TIME SDIO (SD0) VALID TIME
SCLK PULSE WIDTH HIGH/LOW TIME
t
CSU
t
DV
Figure 6. SPI Timing Diagram