Datasheet

AD9726
Rev. B | Page 6 of 24
Parameter Min Typ Max Unit
SERIAL PORT INTERFACE
SCLK Frequency (f
SCLK
) 15 MHz
SCLK Rise/Fall Time 1 ms
SCLK Pulse Width High (t
CPWH
) 30 ns
SCLK Pulse Width Low (t
CPWL
) 30 ns
SCLK Setup Time (t
CSU
) 30 ns
SDIO Setup Time (t
DSU
) 30 ns
SDIO Hold Time (t
DH
) 0 ns
SDIO/SDO Valid Time (t
DV
) 30 ns
RESET PULSE WIDTH 1.5 ns
TIMING DIAGRAMS
DAC CLOCK
DATACLOCK OUTPU
T
DATACLOCK INPUT
DATA BUS
t
DCPD-DDR
t
DSU-DDR
t
DH-DDR
04540-002
Figure 2. DDR Timing Diagram
DAC CLOCK
DATACLOCK OUTPU
T
DATACLOCK INPUT
DATA BUS
t
DCPD-SDR
t
DSU-SDR
t
DH-SDR
04540-003
Figure 3. SDR Timing Diagram
04540-100
DB0 TO DB15
CLK+/CLK–
IOUTA OR IOUTB
t
PD-BYPASS
t
DSU-BYPASS
t
DH-BYPASS
Figure 4. Data Synchronization Bypass Timing Diagram