Datasheet

AD9726
Rev. B | Page 16 of 24
Addr Name Bits I/O Default Description
0x10 MEMADR [7:0] I 00000000 8-bit memory address value for read/write operations.
0x11 MEMDAT [5:0] I/O 000000 6-bit memory data value for read/write operations.
0x15 SYNCOUT [1:0] O 00 2-bit output value indicates current sync quadrant.
0x16 BYPASS 6 I 0 1: bypasses data synchronization circuitry. Data is sampled using the DAC clock (CLK±)
SYNCEXT 5 I 0 1: enables sync external mode; disable auto quadrant select.
SYNCIN [4:3] I 00 2-bit input value is used to specify the sync quadrant.
1
SWRESET also resets itself. SMEM contents are unaffected by SWRESET; however, CALMEM reports an uncalibrated state.
2
EXTREF is optional because the internal reference circuit is designed to be overdriven by an external source.
3
The self-calibration clock is also used for the memory transfer cycle; therefore, the CALCLK value affects the MEMXFER process time.
4
Register Bits 3:0 must all be 0 to assert SELFCAL. The time required for the self-calibration cycle is ~100 ms at 100 MHz with CALCLK = 0.
5
Register Bits 3:0 must all be 0 to assert MEMXFER. The time required for the memory transfer cycle is ~15 ms at 100 MHz with CALCLK = 0.
6
The UNCAL bit remains asserted after the cycle completes (SMEM contents held at default values) until the bit is cleared by the user.