Datasheet

AD9714/AD9715/AD9716/AD9717
Rev. A | Page 49 of 80
DIFFERENTIAL BUFFERED OUTPUT
USING AN OP AMP
A dual op amp (see the circuit shown in Figure 105) can be used
in a differential version of the single-ended buffer shown in
Figure 104. The same RC network is used to form a one-pole
differential, low-pass filter to isolate the op amp inputs from
the high frequency images produced by the DAC outputs. The
feedback resistors, R
FB
, determine the differential peak-to-peak
signal swing by the formula
V
OUT
= 2 × R
FB
× I
FS
The maximum and minimum single-ended voltages out of the
amplifier are, respectively,









B
FB
REFMAX
R
R
VV 1
V
MIN
= V
MAX
− R
FB
× I
FS
The common-mode voltage of the differential output is
determined by the formula
V
CM
= V
MAX
− R
FB
× I
FS
07265-061
AD9714/AD9715/
AD9716/AD9717
IOUTP
IOUTN
R
FB
V
OUT
REFIO
34
28
R
S
AVSS
25
C
F
C
R
FB
R
B
C
F
R
S
R
B
29
+
–
ADA4841-2
+
–
ADA4841-2
Figure 105. Single-Supply Differential Buffer
AUXILIARY DACs
The DACs of the AD9714/AD9715/AD9716/AD9717 feature
two versatile and independent 10-bit auxiliary DACs suitable
for dc offset correction and similar tasks.
Because the AUXDACs are driven through the SPI port, they
should never be used in timing-critical applications, such
as inside analog feedback loops.
To keep the pin count reasonable, these auxiliary DACs each
share a pin with the corresponding FSADJx resistor. They are,
therefore, usable only when enabled and when that DAC is
operated on its internal full-scale resistors. A simple I-to-V
converter is implemented on chip with selectable shunt resistors
(3.2 k to 16 k) such that if REFIO is set to exactly 1 V, REFIO/2
equals 0.5 V and the following equation describes the no load
output voltage:










k16
5.1
V5.0
S
DAC
OUT
R
IV
Figure 106 illustrates the function of all the SPI bits controlling
these DACs with the exception of the QAUXEN (Register 0x0A,
Bit 7) and IAUXEN (Register 0x0C, Bit 7) bits and gating to
prohibit R
S
< 3.2 k.
07265-043
+
–
OP AMP
AUXDAC
[9:0]
A
V
DD
RNG0
RNG1
REFIO
2
16kΩ 16kΩ
16kΩ
4kΩ 8kΩ
OFS2
OFS1
OFS0
(OFS > 4 = 4)
AUX
PIN
RNG: 00 = > 125µA f
S
01 = > 62µA f
S
10 = > 31µA f
S
11 = > 16µA f
S
Figure 106. AUXDAC Simplified Circuit Diagram
The SPI speed limits the update rate of the auxiliary DACs. The
data is inverted such that I
AUXDAC
is full scale at 0x000 and zero
at 0x1FF, as shown in Figure 107.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0 10 20 30 40 50 60 70 80 90 100 120 130
I
AUXDAC
(µA)
OUTPUT (V)
07265-045
110
R
OFFSET
= 3.3kΩ
R
OFFSET
= 4kΩ
R
OFFSET
= 5.3kΩ
R
OFFSET
= 8kΩ
R
OFFSET
= 16kΩ
OP AMP OUTPUT VOLTAGE vs. CHANGES
IN R
OFFSET
AND DAC CURRENT IN µA
Figure 107. AUXDAC Op Amp Output vs. Current, AVDD = 3.3 V, No Load,
AUXDAC 0x1FF to 0x000