Datasheet

AD9714/AD9715/AD9716/AD9717
Rev. A | Page 40 of 80
DIGITAL INTERFACE OPERATION
Digital data for the I and Q DACs is supplied over a single
parallel bus (DB[n:0), where n is 7 for the AD9714, 9 for
the AD9715, 11 for the AD9716, and 13 for the AD9717)
accompanied by a qualifying clock (DCLKIO). The I and Q
data are provided to the chip in an interleaved double data
rate (DDR) format. The maximum guaranteed data rate is
250 MSPS with a 125 MHz clock. The order of data pairing
and the sampling edge selection is user programmable using
the IFIRST and IRISING data control bits, resulting in four
possible timing diagrams. These are shown in Figure 89,
'JHVSF90, Figure 91, and Figure 92.
DCLKIO
ZA B C D E F G H
I DATA Z B D F
Q DATA Y A C E
07265-047
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
D
B[n:0]
Figure 89. Timing Diagram with IFIRST = 0, IRISING = 0
DCLKIO
ZA B C D E F G H
I DATA Y A C E
Q DATA X Z B D
07265-048
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
DB[
n:0]
Figure 90. Timing Diagram with IFIRST = 0, IRISING = 1
DCLKIO
ZA B C D E F G H
I DATA Z B D F
Q DATA A C E G
07265-049
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
DB[n:0]
Figure 91. Timing Diagram with IFIRST = 1, IRISING = 0
DCLKIO
ZA B C D E F G H
I DATA Y A C E
Q DATA Z B D F
07265-050
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
DB[n:0]
Figure 92. Timing Diagram with IFIRST = 1, IRISING = 1
Ideally, the rising and falling edges of the clock fall in the center
of the keep-in-window formed by the setup and hold times, t
S
and t
H
. Refer to Table 2 for setup and hold times. A detailed
timing diagram is shown in Figure 93.
DCLKIO
07265-051
t
S
t
H
t
S
t
H
DB[n:0]
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE
AD9715, 11 FOR THE AD9716, AND 13 FOR THE AD9717.
Figure 93. Setup and Hold Times for All Input Modes
In addition to the different timing modes listed in Table 2, the
input data can also be presented to the device in either unsigned
binary or twos complement format. The format type is chosen
via the TWOS data control bit.