Datasheet

AD9714/AD9715/AD9716/AD9717
Rev. A | Page 32 of 80
THEORY OF OPERATION
I DAC
Q DAC
AUX1DAC
AUX2DAC
BAND
GAP
CLOCK
DIST
10kΩ
QR
SET
16kΩ
IR
SET
16kΩ
I
REF
100µA
IR
CML
1kΩ TO
250Ω
QR
CML
1kΩ TO
250Ω
500Ω
500Ω
500Ω
500Ω
SPI
INTERFACE
1 INTO 2
INTERLEAVED
DATA
INTERFACE
I DATA
Q DATA
1.8V
LDO
1V
AD9717
07265-046
RLIN
IOUTN
IOUTP
RLIP
AVDD
AVSS
RLQP
QOUTP
QOUTN
RLQN
DB11
DB10
DB9
DB8
DVDDIO
DVSS
DVDD
DB7
DB6
DB5
DB12 DB13 (MSB) SDIO/FORMAT SCLK/CLKMD RESET/PINMD REFIO FSADJI/AUXI FSADJQ/AUXQ CMLI
DB4 DB3 DB2 DB1
DB0 (LSB)
DCLKIO
CVDD
CLKIN
CVSS
CMLQ
CS/PW
RDN
Figure 84. Simplified Block Diagram
Figure 84 shows a simplified block diagram of the AD9714/
AD9715/AD9716/AD9717 that consists of two DACs, digital
control logic, and a full-scale output current control. Each DAC
contains a PMOS current source array capable of providing a
nominal full-scale current (I
xOUTFS
) of 2 mA and a maximum of
4 mA. The arrays are divided into 31 equal currents that make
up the five most significant bits (MSBs). The next four bits, or
middle bits, consist of 15 equal current sources whose value is
1/16 of an MSB current source. The remaining LSBs are binary
weighted fractions of the current sources of the middle bits.
Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance
for multitone or low amplitude signals and helps maintain the
high output impedance of the DACs (that is, >200 M).
All of these current sources are switched to one or the other
of the two output nodes (I
OUTP
or I
OUTN
) via PMOS differential
current switches. The switches are based on the architecture that
was pioneered in the AD976x family, with further refinements
to reduce distortion contributed by the switching transient. This
switch architecture also reduces various timing errors and
provides matching complementary drive signals to the inputs
of the differential current switches.
The analog and digital I/O sections of the AD9714/AD9715/
AD9716/AD9717 have separate power supply inputs (AVDD and
DVDDIO) that can operate independently over a 1.8 V to 3.3 V
range. The core digital section requires 1.8 V. An optional on-chip
LDO is provided for DVDDIO supplies greater than 1.8 V, or the
1.8 V can be supplied directly through DVDD. A 1.0 µF bypass
capacitor at DVDD (Pin 7) is required when using the LDO.
The core is capable of operating at a rate of up to 125 MSPS. It
consists of edge-triggered latches and the segment decoding logic
circuitry. The analog section includes PMOS current sources,
associated differential switches, a 1.0 V band gap voltage
reference, and a reference control amplifier.
Each DAC full-scale output current is regulated by the reference
control amplifier and can be set from 1 mA to 4 mA via an external
resistor, xR
SET
, connected to its full-scale adjust pin (FSADJx).
The external resistor, in combination with both the reference
control amplifier and voltage reference, V
REFIO
, sets the reference
current, I
xREF
, which is replicated to the segmented current sources
with the proper scaling factor. The full-scale current, I
xOUTFS
, is
32 × I
xREF
.
Optional on-chip xR
SET
resistors are provided that can be pro-
grammed between a nominal value of 8 k to 32 k (4 mA to
1 mA I
xOUTFS
, respectively).
The AD9714/AD9715/AD9716/AD9717 provide the option of
setting the output common mode to a value other than AVSS
via the output common-mode pins (CMLI and CMLQ). This
facilitates directly interfacing the output of the AD9714/AD9715/
AD9716/AD9717 to components that require common-mode
levels greater than 0 V.