Datasheet

AD9704/AD9705/AD9706/AD9707 Data Sheet
Rev. B | Page 32 of 44
R/WN1N0A4A3A2A1A0D7
N
D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CSB
SCLK
SDIO
05926--091
Figure 72. Serial Register Interface Timing, MSB First Write
R/WN1N0A4A3 A2A1A0
D7
D6
N
D5
N
D0
0
D1
0
D2
0
D3
0
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
05926-090
Figure 73. Serial Register Interface Timing, MSB First Read
A0 A1 A2 A3 A4 N0 N1 R/W D0
0
D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CSB
SCLK
SDIO
05926-089
Figure 74. Serial Register Interface Timing, LSB First Write
INSTRUCTION CYCLE DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
A0 A1 A2 A3 A4 N0 N1 R/W D1
0
D2
0
D7
N
D6
N
D5
N
D4
N
05926-088
D0
Figure 75. Serial Register Interface Timing, LSB First Read
INSTRUCTION BIT 6INSTRUCTION BIT 7
CSB
SCLK
SDIO
t
DS
t
DS
t
DH
t
PWH
t
PWL
t
SCLK
05926-092
Figure 76. Timing Diagram for SPI Register Write
I1 I0 D7 D6 D5
t
HLD
t
SU
CSB
S
CL
K
S
DIO
05926-093
Figure 77. Timing Diagram for SPI Register Read
SPI REGISTER MAP
Table 15.
Mnemonic Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SPI CTL 0x00 SDIODIR DATADIR SWRST LNGINS PDN Sleep CLKOFF EXREF
Data 0x02 DATAFMT DCLKPOL DESKEW CLKDIFF CALCLK
Version 0x0D VER[3] VER[2] VER[1] VER[0]
CALMEM 0x0E CALMEM[1] CALMEM[0] DIVSEL[2] DIVSEL[1] DIVSEL[0]
MEMRDWR 0x0F CALSTAT CALEN SMEMWR SMEMRD UNCAL
MEMADDR 0x10 MEMADDR[5] MEMADDR[4] MEMADDR[3] MEMADDR[2] MEMADDR[1] MEMADDR[0]
MEMDATA 0x11 MEMDATA[5] MEMDATA[4] MEMDATA[3] MEMDATA[2] MEMDATA[1] MEMDATA[0]