Datasheet

AD9704/AD9705/AD9706/AD9707 Data Sheet
Rev. B | Page 10 of 44
DIGITAL SPECIFICATIONS (1.8 V)
T
MIN
to T
MAX
, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, I
OUTFS
= 1 mA, unless otherwise noted.
Table 6.
AD9707 AD9706 AD9705 AD9704
Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
DIGITAL INPUTS
1
Logic 1 Voltage 1.2 1.8 1.2 1.8 1.2 1.8 1.2 1.8 V
Logic 0 Voltage 0 0.5 0 0.5 0 0.5 0 0.5 V
Logic 1 Current −10 +10 −10 +10 −10 +10 −10 +10 μA
Logic 0 Current +10 +10 +10 +10 μA
Input Capacitance 5 5 5 5 pF
Input Setup Time, t
S
, 25°C 2.3 2.3 2.3 2.3 ns
Input Hold Time, t
H
, 25°C 0 0 0 0 ns
Input Setup Time, t
S
, −40°C to +85°C 2.4 2.4 2.4 2.4 ns
Input Hold Time, t
H
, −40°C to +85°C 0.1 0.1 0.1 0.1 ns
Latch Pulse Width, t
LPW
6.2 6.2 6.2 6.2 ns
CLK INPUTS
2
Input Voltage Range 0 1.8 0 1.8 0 1.8 0 1.8 V
Common-Mode Voltage 0.4 0.9 1.3 0.4 0.9 1.3 0.4 0.9 1.3 0.4 0.9 1.3 V
Differential Voltage 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 V
1
Includes CLK+ pin in single-ended clock input mode.
2
Applicable to CLK+ input and CLK– input when configured for differential clock input mode.
TIMING DIAGRAM
DB0 TO DB13
CLOCK
IOUTA
OR
IOUTB
0.1%
0.1%
t
LPW
t
ST
t
PD
t
H
t
S
0
5926-002
Figure 2. Timing Diagram