Datasheet

Data Sheet AD9704/AD9705/AD9706/AD9707
Rev. B | Page 33 of 44
SPI REGISTER DESCRIPTIONS
Table 16. SPI CTL—Register 0x00
Mnemonic Bit No. Direction (I/O) Default Description
SDIODIR 7 I 1 0 = SDIO pin configured for input only during data transfer (4-wire interface).
1 = SDIO pin configured for input or output during data transfer (3-wire interface).
DATADIR 6 I 0 0 = Serial data uses MSB first format.
1 = Serial data uses LSB first format.
SWRST 5 I 0 1 = initiates a software reset; this bit is set to 0 upon reset completion.
LNGINS 4 I 0 0 = uses 1 byte preamble (5 address bits).
1 = uses 2 byte preamble (13 address bits).
PDN 3 I 0 1 = shuts down DAC output current internal band gap reference.
Sleep 2 I 0 1 = DAC output current off.
CLKOFF 1 I 0 1 = disables internal master clock.
EXREF 0 I 0 0 = internal band gap reference.
1 = external reference.
Table 17. Data—Register 0x02
Mnemonic Bit No. Direction (I/O) Default Description
DATAFMT 7 I 0 0 = unsigned binary input data format
1 = twos complement input data format
DCLKPOL 4 I 0 0 = data latched on DATACLK rising edge always
1 = data latched on DATACLK falling edge (only active in DESKEW mode)
DESKEW 3 I 0 0 = DESKEW mode disabled.
1 = DESKEW mode enabled (adds a register in digital data path to remove
skew in received data; one clock cycle of latency is introduced)
CLKDIFF 2 I 0 0 = single-ended clock input
1 = differential clock input
CALCLK 0 I 0 0 = calibration clock disabled
1 = calibration clock enabled
Table 18. Version—Register 0x0D
Mnemonic Bit No. Direction (I/O) Default Description
VER[3:0] [3:0] O 0000 Hardware version identifier
Table 19. CALMEM—Register 0x0E
Mnemonic Bit No. Direction (I/O) Default Description
CALMEM[1:0] [5:4] O 00 Calibration memory
00 = uncalibrated
01 = self-calibration
10 = not used
11 = user input
DIVSEL[2:0] [2:0] I 000 Calibration clock divide ratio from DAC clock rate
000 = divide by 256
001 = divide by 128
…
110 = divide by 4
111 = divide by 2