Datasheet

REV. D
–2–
AD96685/AD96687–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (Positive Supply Voltage = 5.0 V; Negative Supply Voltage = –5.2 V, unless otherwise noted.)
Industrial Temperature Range –25ⴗC to +85ⴗC
Test AD96685BR AD96687BQ/BP/BR
Parameter Temp Level Min Typ Max Min Typ Max Unit
INPUT CHARACTERISTICS
Input Offset Voltage 25°CI 12 12mV
Full VI 3 3 mV
Input Offset Drift Full V 20 20 µV/°C
Input Bias Current 25°CI 710 710µA
Full VI 13 13 µA
Input Offset Current 25°C I 0.1 1.0 0.1 1.0 µA
Full VI 1.2 1.2 µA
Input Resistance 25°C V 200 200 kΩ
Input Capacitance 25°CV 2 2 pF
Input Voltage Ranges
2
Full VI –2.5 +5.0 –2.5 +5.0 V
Common-Mode Rejection Ratio Full VI 80 90 80 90 dB
ENABLE INPUT
Logic “1” Voltage Full VI –1.1 –1.1 V
Logic “0” Voltage Full VI –1.5 –1.5 V
Logic “1” Current Full VI 40 40 µA
Logic “0” Current Full VI 5 5 µA
DIGITAL OUTPUTS
3
Logic “1” Voltage Full VI –1.1 –1.1 V
Logic “0” Voltage Full VI –1.5 –1.5 V
SWITCHING PERFORMANCES
Propagation Delays
4
Input to Output HIGH 25°C IV 2.5 3.5 2.5 3.5 ns
Input to Output LOW 25°C IV 2.5 3.5 2.5 3.5 ns
Latch Enable to Output HIGH 25°C IV 2.5 3.5 2.5 3.5 ns
Latch Enable to Output LOW 25°C IV 2.5 3.5 2.5 3.5 ns
Dispersions
5
25°C V 50 50 ps
Latch Enable
Minimum Pulsewidth 25°C IV 2.0 3.0 2.0 3.0 ns
Minimum Setup Time 25°C IV 0.5 1.0 0.5 1.0 ns
Minimum Hold Time 25°C IV 0.5 1.0 0.5 1.0 ns
POWER SUPPLY
6
Positive Supply Current (+5.0 V) Full VI 8 9 15 18 mA
Negative Supply Current (–5.2 V) Full VI 15 18 31 36 mA
Power Supply Rejection Ratio
7
Full VI 60 70 60 70 dB
NOTES
1
R
S
= 100 Ω.
2
Input Voltage Range can be extended to –3.3 V if –V
S
= –6.0 V.
3
Outputs terminated through 50 Ω to –2.0 V.
4
Propagation delays measured with 100 mV pulse (10 mV overdrive) to 50% transition point of the output.
5
Change in propagation delay from 100 mV to 1 V input overdrive.
6
Supply voltages should remain stable within ± 5% for normal operation.
7
Measured at ± 5% of +V
S
and –V
S
.
Specifications subject to change without notice.
COMPARE
LATCH
LATCH
ENABLE
DIFFERENTIAL
INPUT
VO LTAG E
50%
V
OS
50%
50%
t
S
V
IN
V
DD
t
H
t
PW
(E)
t
PD
(E)
t
PD
Q
Q
t
S
t
H
t
PD
t
PD
(E)
t
PW
(E)
V
OS
V
OD
– Minimum Setup Time
– Minimum Hold Time
– Input to Output Delay
– LATCH ENABLE to Output Delay
– Minimum LATCH ENABLE Pulsewidth
– Input Offset Voltage
– Overdrive Voltage
Figure 1. System Timing Diagram