Datasheet

AD9649

Rev. 0 | Page 29 of 32

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Note, Interfacing to High Speed ADCs via SPI.

USR2 (Register 0x101)

Bit 3—Enable GCLK Detect

Normally set high, Bit 3 enables a circuit that detects encode

rates below ~5 MSPS. When a low encode rate is detected, an

internal oscillator, GCLK, is enabled, ensuring the proper oper-

ation of several circuits. If set low, the detector is disabled.

Bit 2—Run GCLK

Bit 2 enables the GCLK oscillator. For some applications with

encode rates below 10 MSPS, it may be preferable to set this bit

high to supersede the GCLK detector.

Bit 0—Disable SDIO Pull-Down

Bit 0 can be set high to disable the internal 30 k pull-down on

the SDIO pin, which can be used to limit the loading when many

devices are connected to the SPI bus.