Datasheet

AD9649
Rev. 0 | Page 25 of 32
HARDWARE INTERFACE
The pins described in Table 13 constitute the physical interface
between the programming device of the user and the serial port
of the AD9649. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. For detailed information about one
method for SPI configuration, refer to the AN-812 Application
Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between this
bus and the AD9649 to prevent these signals from transitioning
at the converter inputs during critical sampling periods.
The SDIO/PDWN and SCLK/DFS pins serve a dual function when
the SPI interface is not being used. When the pins are strapped
to DRVDD or ground during device power-on, they are associated
with a specific function. The Digital Outputs section describes
the strappable functions supported on the AD9649.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/PDWN pin and the SCLK/DFS pin serve as standalone
CMOS-compatible control pins. When the device is powered up, it
is assumed that the user intends to use the pins as static control
lines for the power-down and output data format feature control.
In this mode, connect the CSB chip select to DRVDD, which
disables the serial port interface.
Table 14. Mode Selection
Pin
External
Voltage Configuration
SDIO/PDWN DRVDD Chip power-down mode
AGND (default) Normal operation (default)
SCLK/DFS DRVDD Twos complement enabled
AGND (default) Offset binary enabled
SPI ACCESSIBLE FEATURES
Tabl e 15 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9649 part-specific features are described in detail
in Table 16.
Table 15. Features Accessible Using the SPI
Feature Description
Modes
Allows the user to set either power-down mode or
standby mode
Offset Adjust
Allows the user to digitally adjust the converter
offset
Test Mode
Allows the user to set test modes to have known
data on output bits
Output Mode Allows the user to set up outputs
Output Phase Allows the user to set the output clock polarity
Output Delay Allows the user to vary the DCO delay