Datasheet

AD9649
Rev. 0 | Page 10 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1CLK+
2CLK–
3AVDD
4CSB
5SCLK/DFS
6SDIO/PDWN
7D0 (LSB)
8D1
24 AVDD
23 MODE/OR
22 DCO
21 D13 (MSB)
20 D12
19 D11
18 D10
17 D9
9
D2
10
D3
11
D4
12
D5
13
DRVDD
14
D6
15
D7
16
D
8
32
AVDD
31
VIN+
30
VIN–
29
AVDD
28
RBIAS
27
VCM
26
SENSE
25
VREF
TOP VIEW
(Not to Scale)
AD9649
08539-003
NOTES
1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE ANALOG GROUND
PLANE OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND MAXIMIZE
THE HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
0 (EP) GND
Exposed Paddle. The exposed paddle is the only ground connection. It must be soldered to the analog
ground of the customer’s PCB to ensure proper functionality and maximize the heat dissipation, noise,
and mechanical strength benefits.
1, 2 CLK+, CLK− Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs.
3, 24, 29, 32 AVDD 1.8 V Supply Pin for the ADC CORE Domain.
4 CSB SPI Chip Select. Active low enable, 30 kΩ internal pull-up.
5 SCLK/DFS
SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.
Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.
DFS high = twos complement output; DFS low = offset binary output.
6 SDIO/PDWN
SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.
Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-down.
See Table 14 for details.
7 to 12, 14 to 21
D0 (LSB) to
D13 (MSB)
ADC Digital Outputs.
13 DRVDD 1.8 V to 3.3 V Supply Pin for Output Driver Domain.
22 DCO Data Clock Digital Output.
23 MODE/OR Chip Mode Select Input in SPI Mode (MODE).
Out-of-Range Digital Output in SPI Mode or in Non-SPI Mode (OR).
Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1).
Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0).
Chip power-down (SPI Register 0x08, Bits[7:5] = 100).
Chip stand-by (SPI Register 0x08, Bits[7:5] = 101).
Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110).
Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111).
In non-SPI mode, the pin operates only as an out-of-range (OR) digital output.
25 VREF 1.0 V Voltage Reference Input/Output. See Table 10.
26 SENSE Reference Mode Selection. See Table 10.
27 VCM Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.
28 RBIAS Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
30, 31 VIN−, VIN+ ADC Analog Inputs.