Datasheet

AD9648
Rev. 0 | Page 18 of 44
Pin No. Mnemonic Type Description
Digital Outputs
8 B D1−/D0− (LSB) Output Channel B LVDS Output Data 1/Data 0—Complement.
9 B D1+/D0+ (LSB) Output Channel B LVDS Output Data 1/Data 0—True.
11 B D3−/D2− Output Channel B LVDS Output Data 3/Data 2—Complement.
12 B D3+/D2+ Output Channel B LVDS Output Data 3/Data 2—True.
13 B D5−/D4− Output Channel B LVDS Output Data 5/Data 4—Complement.
14 B D5+/D4+ Output Channel B LVDS Output Data 5/Data 4—True.
15 B D7−/D6− Output Channel B LVDS Output Data 7/Data 6—Complement.
16 B D7+/D6+ Output Channel B LVDS Output Data 7/Data 6—True.
17 B D9−/D8− Output Channel B LVDS Output Data 9/Data 8—Complement.
18 B D9+/D8+ Output Channel B LVDS Output Data 9/Data 8—True.
20 B D11−/D10− Output Channel B LVDS Output Data 11/Data 10—Complement.
21 B D11+/D10+ Output Channel B LVDS Output Data 11/Data 10—True.
22 B D13−/D12− (MSB) Output Channel B LVDS Output Data 13/Data 12—Complement.
23 B D13+/D12+ (MSB) Output Channel B LVDS Output Data 13/Data 12—True.
26 A D1−/D0− (LSB) Output Channel A LVDS Output Data 1/Data 0—Complement.
27 A D1+/D0+ (LSB) Output Channel A LVDS Output Data 1/Data 0—True.
29 A D3−/D2− Output Channel A LVDS Output Data 3/Data 2—Complement.
30 A D3+/D2+ Output Channel A LVDS Output Data 3/Data 2—True.
32 A D5+/D4+ Output Channel A LVDS Output Data 5/Data 4—Complement.
31 A D5−/D4− Output Channel A LVDS Output Data 5/Data 4—True.
34 A D7+/D6+ Output Channel A LVDS Output Data 7/Data 6—Complement.
33 A D7−/D6− Output Channel A LVDS Output Data 7/Data 6—True.
36 A D9+/D8+ Output Channel A LVDS Output Data 9/Data 8—Complement.
35 A D9−/D8− Output Channel A LVDS Output Data 9/Data 8—True.
39 A D11+/D10+ Output Channel A LVDS Output Data 11/Data 10—Complement.
38 A D11−/D10− Output Channel A LVDS Output Data 11/Data 10—True.
41 A D13+/D12+ (MSB) Output Channel A LVDS Output Data 13/Data 12—Complement.
40 A D13−/D12− (MSB) Output Channel A LVDS Output Data 13/Data 12—True.
43 OR+ Output Channel A/Channel B LVDS Overrange Output—True.
42 OR− Output Channel A/Channel B LVDS Overrange Output—Complement.
25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True.
24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement.
SPI Control
45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode.
44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
46 CSB Input SPI Chip Select (Active Low).
ADC Configuration
47 OEB Input Output Enable Input (Active Low). Pin must be enabled via SPI.
48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be
configured as power-down or standby.