Datasheet

AD9648
Rev. 0 | Page 10 of 44
t
PD
t
SKEW
t
CH
t
DCO
t
CLK
CH A
N – 16
CH B
N – 15
CH A
N – 14
CH B
N – 13
CH A
N – 12
CH B
N – 11
CH A
N – 10
CH B
N – 9
CH A
N – 8
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
VIN
CLK+
CLK–
CH A DATA
DCOA/DCOB
t
A
CH B DATA
CH B
N – 16
CH A
N – 15
CH B
N – 14
CH A
N – 13
CH B
N – 12
CH A
N – 11
CH B
N – 10
CH A
N – 9
CH B
N – 8
09975-003
Figure 3. CMOS Interleaved Output Mode Data Output Timing
t
PD
t
SKEW
t
CH
t
DCO
t
CLK
CH A
N – 12
CH B
N – 12
CH A
N – 11
CH B
N – 11
CH A
N – 10
CH B
N – 10
CH A
N – 9
CH B
N – 9
CH A
N – 8
N – 1
N + 1
N + 2
N + 3
N + 5
N + 4
N
VIN
CLK+
CLK–
DCO+
DCO–
D0+ (LSB)
PARALLEL
INTERLEAVED
MODE
D0– (LSB)
D13+ (MSB)
D13– (MSB)
t
A
CH A
N – 12
CH B
N – 12
CH A
N – 11
CH B
N – 11
CH A
N – 10
CH B
N – 10
CH A
N – 9
CH B
N – 9
CH A
N – 8
CH A0
N – 12
CH A1
N – 12
CH A0
N – 11
CH A1
N – 11
CH A0
N – 10
CH A1
N – 10
CH A0
N – 9
CH A1
N – 9
CH A0
N – 8
D1+/0+ (LSB)
CHANNEL
MULTIPLEXED
MODE
CHANNEL A
D1–/D0– (LSB)
D13+/D12+ (MSB)
D13–/D12– (MSB)
CH A12
N – 12
CH A13
N – 12
CH A12
N – 11
CH A13
N – 11
CH A12
N – 10
CH A13
N – 10
CH A12
N – 9
CH A13
N – 9
CH A12
N – 8
CH B0
N – 12
CH B1
N – 12
CH B0
N – 11
CH B1
N – 11
CH B0
N – 10
CH B1
N – 10
CH B0
N – 9
CH B1
N – 9
CH B0
N – 8
D1+/D0+ (LSB)
CHANNEL
MULTIPLEXED
MODE
CHANNEL B
D1–/D0– (LSB)
D13+/D12+ (MSB)
D13–/D12– (MSB)
CH B12
N – 12
CH B13
N – 12
CH B12
N – 11
CH B13
N – 11
CH B12
N – 10
CH B13
N – 10
CH A12
N – 9
CH A13
N – 9
CH A12
N – 8
09975-004
Figure 4. LVDS Modes for Data Output Timing