Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LFCSP 64 VQ

14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual

Analog-to-Digital Converter

AD9648

Rev.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113 ©

FEATURES

1.8 V analog supply operation

1.8 V CMOS or LVDS outputs

SNR = 74.5 dBFS @ 70 MHz

SFDR = 91 dBc @ 70 MHz

Low power: 78 mW/channel ADC core @ 125 MSPS

Differential analog input with 650 MHz bandwidth

IF sampling frequencies to 200 MHz

On-chip voltage reference and sample-and-hold circuit

2 V p-p differential analog input

DNL = ±0.35 LSB

Serial port control options

Offset binary, gray code, or twos complement data format

Optional clock duty cycle stabilizer

Integer 1-to-8 input clock divider

Data output multiplex option

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock out with programmable clock and data

alignment

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers

GSM, EDGE, W-CDMA, LT E,

CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems

Smart antenna systems

Broadband data applications

Battery-powered instruments

Hand held scope meters

Portable medical imaging

Ultrasound

Radar/LIDAR

This product is protected by a U.S patent.

FUNCTIONAL BLOCK DIAGRAM

VIN+A

VIN–A

VREF

SENSE

VCM

RBIAS

VIN–B

VIN+B

ORA

D0A

D13A

DCOA

DRVDD

ORB

D13B

D0B

DCOB

SDIOAGNDAVDD SCLK

SPI

PROGRAMMING DATA

MUX OPTION

PDWN DFSCLK+ CLK–

MODE

CONTROLS

DCS

DUTY CYCLE

STABILIZER

SYNC

DIVIDE

1 TO 8

OEB

CSB

REF

SELECT

ADC

CMOS/LVDS

OUTPUT BUFFER

ADC

CMOS/LVDS

OUTPUT BUFFER

AD9648

09975-001

NOTES

1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;

SEE FIGURE 7 FORLVDS PIN NAMES.

Figure 1.

PRODUCT HIGHLIGHTS

1. The AD9648

operates from a single 1.8 V analog

power supply and features a separate digital output

driver supply to accommodate 1.8 V CMOS or LVDS

logic families.

2. The patented sample-and-hold circuit maintains

excellent performance for input frequencies up to

200 MHz and is designed for low cost, low power, and

ease of use.

3. A standard serial port interface supports various

product features and functions, such as data output

formatting, internal clock divider, power-down,

DCO/data timing and offset adjustments.

4. The AD9648 is packaged in a 64-lead RoHS compliant

LFCSP that is pin compatible with the AD9650/

AD9269/AD9268 16-bit ADC, the AD9258 14-bit

ADC, the AD9628/AD9231 12-bit ADCs, and the

AD9608/AD9204 10-bit ADCs, enabling a simple

migration path between 10-bit and 16-bit converters

sampling from 20 MSPS to 125 MSPS.

Summary of content (44 pages)

PAGE 1
4-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9648 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation 1.8 V CMOS or LVDS outputs SNR = 74.5 dBFS @ 70 MHz SFDR = 91 dBc @ 70 MHz Low power: 78 mW/channel ADC core @ 125 MSPS Differential analog input with 650 MHz bandwidth IF sampling frequencies to 200 MHz On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.
PAGE 2
AD9648 TABLE OF CONTENTS Features .............................................................................................. 1 Voltage Reference ....................................................................... 27 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 28 Functional Block Diagram ..............................................................
PAGE 3
AD9648 GENERAL DESCRIPTION The AD9648 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and onchip voltage reference. A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.
PAGE 4
AD9648 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) 1 Integral Nonlinearity (INL)1 MATCHING CHARACTERISTIC Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Load Regulation Error at 1.
PAGE 5
AD9648 Parameter POWER CONSUMPTION DC Input Sine Wave Input (DRVDD = 1.8 V CMOS Output Mode) Sine Wave Input (DRVDD = 1.8 V LVDS Output Mode) Standby Power3 Power-Down Power 1 2 3 Temp Min AD9648-105 Typ Max Min AD9648-125 Typ Max Unit Full Full 135.4 172.3 181.3 155.5 202.5 211.5 mW mW Full 180.4 189.4 211.5 220.5 mW Full Full 108 2.0 120 2.0 mW mW Measure with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
PAGE 6
AD9648 Parameter1 SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz fIN = 30.
PAGE 7
AD9648 Parameter LOGIC INPUT (SCLK/DFS/SYNC)2 High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 1.8 V) Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT/OUTPUT (SDIO/DCS)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (OEB, PDWN)2 High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 1.
PAGE 8
AD9648 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate1 DCS Enabled DCS Disabled CLK Period—Divide-by-1 Mode (tCLK) CLK Pulse Width High (tCH) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) DATA OUTPUT PARAMETERS CMOS Mode (DRVDD = 1.
PAGE 9
AD9648 TIMING SPECIFICATIONS Table 5. Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Description Limit Unit SYNC to rising edge of CLK+ setup time SYNC to rising edge of CLK+ hold time 0.24 0.
PAGE 10
AD9648 N–1 N+4 tA N+5 N N+3 VIN N+1 tCH N+2 tCLK CLK+ CLK– tDCO DCOA/DCOB tSKEW CH A CH B CH A CH B CH A N – 16 N – 15 N – 14 N – 13 N – 12 CH B CH A N – 11 N – 10 CH B N–9 CH A N–8 CH B CH A CH B CH A CH B CH A CH B N – 16 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 CH A N–9 CH B N–8 CH A DATA CH B DATA 09975-003 tPD Figure 3.
PAGE 11
AD9648 CLK+ tHSYNC 09975-005 tSSYNC SYNC Figure 5. SYNC Input Timing Requirements Rev.
PAGE 12
AD9648 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Electrical1 AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB PDWN D0A/D0B through D13A/D13B to AGND DCOA/DCOB to AGND Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) 1 Rating −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to AVDD + 0.2 V −0.
PAGE 13
AD9648 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VIN–B AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VIN–A VIN+A AVDD AVDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9648 PARALLEL CMOS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDWN OEB CSB SCLK/DFS SDIO/DCS ORA D13A (MSB) D12A D11A D10A D9A DRVDD D8A D7A D6A D5A NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2.
PAGE 14
AD9648 Pin No.
PAGE 15
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VIN–B AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VIN–A VIN+A AVDD AVDD AD9648 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9648 INTERLEAVED PARALLEL LVDS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDWN OEB CSB SCLK/DFS SDIO/DCS OR+ OR– D13+ (MSB) D13– (MSB) D12+ D12– DRVDD D11+ D11– D10+ D10– NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2.
PAGE 16
AD9648 Pin No.
PAGE 17
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VIN–B AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VIN–A VIN+A AVDD AVDD AD9648 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9648 CHANNEL MULTIPLEXED LVDS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDWN OEB CSB SCLK/DFS SDIO/DCS OR+ OR– A D13+/D12+ (MSB) A D13–/D12– (MSB) A D11+/D10+ A D11–/D10– DRVDD A D9+/D8+ A D9–/D8– A D7+/D6+ A D7–/D6– NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2.
PAGE 18
AD9648 Pin No.
PAGE 19
AD9648 TYPICAL PERFORMANCE CHARACTERISTICS AD9648-125 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. 0 –40 –60 –80 –40 –60 –80 10 20 30 40 50 –120 09975-014 0 60 FREQUENCY (MHz) 0 30 40 50 0 125MSPS 30.5MHz AT –1dBFS SNR = 74.0dB (75.0dBFS) –20 SFDR = 86.0dBc 125MSPS 200.5MHz AT –1dBFS SNR = 70.9dB (71.9dBFS) SFDR = 83.
PAGE 20
AD9648 AD9648-125 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. 0 –10 SFDR (dBc) –15 SFDR/IMD3 (dBc/dBFS) –30 AMPLITUDE (Hz) –45 –60 –75 2F1 – F2 2F2 – F1 2F1 + F2 –90 –105 –120 –30 IMD3(dBc) –50 –70 –90 SFDR (dBFS) –135 IMD3 (dBFS) –110 –90 Figure 14.
PAGE 21
2.0 1.5 1.5 1 1.0 0.5 0 –0.5 0.5 0 -0.5 –1.0 –1.0 –1.5 –1.5 –2.0 0 2000 4000 6000 8000 10000 12000 14000 16000 OUTPUT CODE –2.0 450,000 400,000 350,000 300,000 250,000 200,000 150,000 100,000 50,000 09975-074 N+6 N+5 N+4 N+3 N+2 N+1 N N–1 N–2 N–3 N–4 N–5 0 N–6 NUMBER OF HITS 2000 4000 6000 8000 10000 12000 14000 16000 OUTPUT CODE Figure 22. INL Error with fIN = 9.7 MHz Figure 20. DNL Error with fIN = 9.7 MHz OUTPUT CODE 0 Figure 21.
PAGE 22
AD9648 AD9648-105 AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. 0 –40 –60 –80 –40 –60 –80 10 20 30 40 50 FREQUENCY (MHz) –120 09975-014 0 10 20 30 40 50 FREQUENCY (MHz) Figure 26. Single-Tone FFT with fIN = 100.5 MHz Figure 23. Single-Tone FFT with fIN = 9.7 MHz 0 0 105MSPS 30.5MHz AT –1dBFS SNR = 74.5dB (75.5dBFS) SFDR = 89.9dBc 105MSPS 200.5MHz AT –1dBFS SNR = 69.5dB (70.
PAGE 23
AD9648 100 120 95 SFDRFS SFDR (dBc) 100 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 90 85 80 SNR (dBFS) 75 70 65 SNRFS 80 60 SFDR 40 SNR 60 20 0 50 100 150 200 250 ANALOG INPUT FREQUENCY (MHz) 0 –90 09975-075 50 –40 –30 –20 0 –10 SFDR (dBc) SNR (dBFS) 80 100 SFDR (dBc) 80 SNR (dBFS) SNR/SFDR (dBFS/dBc) 60 40 60 40 20 15 25 35 45 55 65 75 85 95 105 SAMPLE RATE (MSPS) 0 09975-012 5 5 1.5 1.5 1.0 1.0 INL ERROR (LSB) 2.0 0.5 0 –0.
PAGE 24
AD9648 EQUIVALENT CIRCUITS DRVDD AVDD 350Ω SCLK/DFS, SYNC, OEB, AND PDWN 30kΩ 09975-039 09975-045 VIN±x Figure 38. Equivalent SCLK/DFS, SYNC, OEB, and PDWN Input Circuit Figure 34. Equivalent Analog Input Circuit AVDD 5Ω CLK+ 15kΩ 375Ω SENSE 09975-043 0.9V 15kΩ 5Ω 09975-040 CLK– Figure 39. Equivalent SENSE Circuit Figure 35. Equivalent Clock Input Circuit DRVDD DRVDD AVDD PAD 30kΩ 09975-047 09975-044 CSB 350Ω Figure 40. Equivalent CSB Input Circuit Figure 36.
PAGE 25
AD9648 THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS The analog input to the AD9648 is a differential switchedcapacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance.
PAGE 26
AD9648 Input Common Mode driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. The analog inputs of the AD9648 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide a dc bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 43.
PAGE 27
AD9648 In any configuration, the value of Shunt Capacitor C is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 11 displays the suggested values to set the RC network. However, these values are dependent on the input signal and should be used only as a starting guide. the reference amplifier switch is connected to the internal resistor divider (see Figure 49), setting VREF to 1.0 V. VIN+A/VIN+B VIN–A/VIN–B Table 11.
PAGE 28
AD9648 External Reference Operation Clock Input Options The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 51 shows the typical drift characteristics of the internal reference in 1.0 V mode. The AD9648 has a very flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal.
PAGE 29
AD9648 If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 55. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer excellent jitter performance. 0.1µF CLK+ 0.1µF AD951x PECL DRIVER CLOCK INPUT 100Ω ADC 0.1µF 50kΩ 240Ω 50kΩ 09975-061 CLK– 240Ω Figure 55.
PAGE 30
AD9648 Jitter Considerations primarily by the strength of the digital drivers and the load on each output bit. High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR from the low frequency SNR (SNRLF) at a given input frequency (fINPUT) due to jitter (tJRMS) can be calculated by The maximum DRVDD current (IDRVDD) can be calculated as IDRVDD = VDRVDD × CLOAD × fCLK × N where N is the number of output bits (30, in the case of the AD9648).
PAGE 31
AD9648 The AD9648 is placed in power-down mode either by the SPI port or by asserting the PDWN pin high. In this state, the ADC typically dissipates less than 2 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9648 to its normal operating mode. Note that PDWN is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage.
PAGE 32
AD9648 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9648 includes a built-in test feature designed to enable verification of the integrity of each channel, as well as to facilitate board level debugging. A built-in self-test (BIST) feature that verifies the integrity of the digital datapath of the AD9648 is included. Various output test options are also provided to place predictable values on the outputs of the AD9648.
PAGE 33
AD9648 SERIAL PORT INTERFACE (SPI) The AD9648 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port.
PAGE 34
AD9648 HARDWARE INTERFACE The pins described in Table 15 comprise the physical interface between the user programming device and the serial port of the AD9648. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers.
PAGE 35
AD9648 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel index and transfer registers (Address 0x05 and Address 0xFF) and the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x102).
PAGE 36
AD9648 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 18 are not currently supported for this device. Table 18.
PAGE 37
AD9648 Addr (Hex) 0x0B Register Name Clock divide (global) Bit 7 (MSB) Open Bit 6 Open Bit 5 Open Bit 4 Open Bit 3 Open 0x0C Enhancement control (global) Open Open Open Open Open 0x0D Test mode (local) User test mode control 00 = single pattern mode 01 = alternate continuous/repeat pattern mode 10 = single once pattern mode 11 = alternate once pattern mode Reset PN long gen Reset PN short gen 0x0E BIST enable (global) Customer offset adjust (local) Output mode Open Open Open 0x10 0x
PAGE 38
AD9648 Default Value (Hex) 0x04 Addr (Hex) 0x18 Register Name VREF select (global) Bit 7 (MSB) Open Bit 6 Open Bit 5 Open Bit 4 Open Bit 3 Open 0x19 User Pattern 1 LSB (global) User Pattern 1 MSB (global) User Pattern 2 LSB (global) User Pattern 2 MSB B7 B6 B5 B4 B3 Bit 0 Bit 2 Bit 1 (LSB) Internal VREF digital adjustment 000 = 1.0 V p-p 001 = 1.14 V p-p 010 = 1.33 V p-p 011 = 1.6 V p-p 100 = 2.
PAGE 39
AD9648 MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. interleaving feature. Channel A is sent on least significant bits (LSBs), and Channel B is sent on most significant bits (MSBs). The even bits are sent coincident with a high DCO clock, and the odd bits are sent coincident with a low DCO clock.
PAGE 40
AD9648 User I/O Control 2 (Register 0x101) Bit 7—OEB Pin Enable User I/O Control 3 (Register 0x102) Bits[7:4]—Open If the OEB pin enable bit (Bit 7) is set, the OEB pin is enabled. If Bit 7 is clear, the OEB pin is disabled (default). Bit 3—VCM Power-Down Bits[6:1]—Open Bit 0—SDIO Pull-Down Bit 0 can be set to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus.
PAGE 41
AD9648 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9648 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for certain pins. Power and Ground Recommendations When connecting power to the AD9648, it is recommended that two separate 1.8 V supplies be used. Use one supply for analog (AVDD); use a separate supply for the digital outputs (DRVDD).
PAGE 42
AD9648 OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 64 49 48 PIN 1 INDICATOR 1 PIN 1 INDICATOR 8.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 SEATING PLANE 33 32 16 17 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 0.05 MAX 0.02 NOM 0.30 0.23 0.18 6.35 6.20 SQ 6.05 EXPOSED PAD (BOTTOM VIEW) 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
PAGE 43
AD9648 NOTES Rev.