Datasheet

Data Sheet AD9645
Rev. 0 | Page 9 of 36
D0x–
D0x+
FCO–
DCO+
CLK+
VINx±
CLK–
DCO–
FCO+
D12
N – 17
MSB
N – 17
D11
N – 17
D10
N – 17
D9
N – 17
D8
N – 17
D7
N – 17
D6
N – 17
D5
N – 17
D4
N – 17
D3
N – 17
D2
N – 17
D1
N – 17
LSB
N – 17
0
N – 17
0
N – 17
MSB
N – 16
D14
N – 16
D13
N – 16
t
A
t
DATA
t
EH
t
FCO
t
FRAME
t
PD
t
CPD
t
EL
N – 1
N
10537-006
Figure 6. Wordwise DDR, One-Lane, 1× Frame, 16-Bit Output Mode
D0x–
D0x+
FCO–
DCO+
CLK+
VINx±
CLK–
DCO–
FCO+
D10
N – 17
MSB
N – 17
D9
N – 17
D8
N – 17
D7
N – 17
D6
N – 17
D5
N – 17
D4
N – 17
D3
N – 17
D2
N – 17
D1
N – 17
D0
N – 17
MSB
N – 16
D10
N – 16
t
A
t
DATA
t
EH
t
FCO
t
FRAME
t
PD
t
CPD
t
EL
N – 1
N
10537-007
Figure 7. Wordwise DDR, One-Lane, 1× Frame, 12-Bit Output Mode