Datasheet

Data Sheet AD9645
Rev. 0 | Page 5 of 36
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 3.
Parameter
1
Temp Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage
2
Full 0.2 3.6 V p-p
Input Voltage Range Full AGND − 0.2 AVDD + 0.2 V
Input Common-Mode Voltage Full 0.9 V
Input Resistance (Differential) 25°C 15 kΩ
Input Capacitance 25°C 4 pF
LOGIC INPUT (SCLK/DFS)
Logic 1 Voltage
Full
1.2
AVDD + 0.2
V
Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF
LOGIC INPUT (CSB)
Logic 1 Voltage Full 1.2 AVDD + 0.2 V
Logic 0 Voltage Full 0 0.8 V
Input Resistance 25°C 26 kΩ
Input Capacitance 25°C 2 pF
LOGIC INPUT (SDIO/PDWN)
Logic 1 Voltage Full 1.2 AVDD + 0.2 V
Logic 0 Voltage
Full
0
0.8
V
Input Resistance 25°C 26 kΩ
Input Capacitance 25°C 5 pF
LOGIC OUTPUT (SDIO/PDWN)
3
Logic 1 Voltage (I
OH
= 800 μA) Full 1.79 V
Logic 0 Voltage (I
OL
= 50 μA) Full 0.05 V
DIGITAL OUTPUTS (D0x±, D1x±), ANSI-644
Logic Compliance LVDS
Differential Output Voltage Magnitude (V
OD
) Full 290 345 400 mV
Output Offset Voltage (V
OS
) Full 1.15 1.25 1.35 V
Output Coding (Default) Twos complement
DIGITAL OUTPUTS (D0x±, D1x±), LOW POWER,
REDUCED SIGNAL OPTION
Logic Compliance LVDS
Differential Output Voltage Magnitude (V
OD
) Full 160 200 230 mV
Output Offset Voltage (V
OS
) Full 1.15 1.25 1.35 V
Output Coding (Default) Twos complement
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
Specified for LVDS and LVPECL only.
3
Specified for 13 SDIO/PDWN pins sharing the same connection.