Datasheet

AD9645 Data Sheet
Rev. 0 | Page 34 of 36
Bits[3:0]—Output Clock Phase Adjust
See Table 19 for details.
Table 19. Output Clock Phase Adjust Options
Output Clock (DCO),
Phase Adjust, Bits[3:0]
DCO Phase Adjustment (Degrees
Relative to D0x±/D1x± Edge)
0000 0
0001 60
0010 120
0011 (Default) 180
0100 240
0101 300
0110 360
0111 420
1000 480
1001 540
1010 600
1011 660
Serial Output Data Control (Register 0x21)
The serial output data control register is used to program the
AD9645 in various output data modes, depending on the data
capture solution. Table 20 describes the various serialization
options available in the AD9645.
Resolution/Sample Rate Override (Register 0x100)
This register is designed to allow the user to downgrade the device.
Any attempt to upgrade the default speed grade results in a chip
power-down. Settings in this register are not initialized until Bit 0
of the transfer register (Register 0xFF) is written high.
User I/O Control 2 (Register 0x101)
Bits[7:1]—Open
Bit 0—SDIO Pull-Down
Bit 0 can be set to disable the internal 30 kΩ pull-down on the
SDIO pin, which can be used to limit the loading when many
devices are connected to the SPI bus.
User I/O Control 3 (Register 0x102)
Bits[7:4]—Open
Bit 3—VCM Power-Down
Bit 3 can be set high to power down the internal VCM generator.
This feature is used when applying an external reference.
Bits[2:0]—Open
Table 20. SPI Register Options
Serialization Options Selected
Register 0x21
Contents
Serial Output Number
of Bits (SONB) Frame Mode Serial Data Mode DCO Multiplier Timing Diagram
0x30 16-bit 1× DDR two-lane bytewise 4 × f
S
See Figure 2 (default setting)
0x20 16-bit 1× DDR two-lane bitwise 4 × f
S
See Figure 2
0x10 16-bit 1× SDR two-lane bytewise 8 × f
S
See Figure 2
0x00 16-bit 1× SDR two-lane bitwise 8 × f
S
See Figure 2
0x34 16-bit 2× DDR two-lane bytewise 4 × f
S
See Figure 4
0x24 16-bit 2× DDR two-lane bitwise 4 × f
S
See Figure 4
0x14 16-bit 2× SDR two-lane bytewise 8 × f
S
See Figure 4
0x04
16-bit
2×
SDR two-lane bitwise
8 × f
S
See Figure 4
0x40 16-bit 1× DDR one-lane wordwise 8 × f
S
See Figure 6
0x32 12-bit 1× DDR two-lane bytewise 3 × f
S
See Figure 3
0x22 12-bit 1× DDR two-lane bitwise 3 × f
S
See Figure 3
0x12 12-bit 1× SDR two-lane bytewise 6 × f
S
See Figure 3
0x02 12-bit 1× SDR two-lane bitwise 6 × f
S
See Figure 3
0x36 12-bit 2× DDR two-lane bytewise 3 × f
S
See Figure 5
0x26 12-bit 2× DDR two-lane bitwise 3 × f
S
See Figure 5
0x16 12-bit 2× SDR two-lane bytewise 6 × f
S
See Figure 5
0x06 12-bit 2× SDR two-lane bitwise 6 × f
S
See Figure 5
0x42 12-bit 1× DDR one-lane wordwise 6 × f
S
See Figure 7