Datasheet

Data Sheet AD9645
Rev. 0 | Page 31 of 36
Addr.
(Hex)
Parameter Name
Bit 7
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Comments
0x0D Test mode
(local except for
PN sequence
resets)
User input test mode
00 = single
01 = alternate
10 = single once
11 = alternate once
(affects user input
test mode only,
Bits[3:0] = 1000)
Reset PN
long gen
Reset PN
short
gen
Output test mode, Bits[3:0] (local)
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN23 sequence
0110 = PN9 sequence
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
0x00 When set, the
test data is
placed on the
output pins
in place of
normal data.
0x10
Offset adjust
(local)
8-bit device offset adjustment, Bits[7:0] (local)
Offset adjust in LSBs from +127 to −128 (twos complement format)
0x00
Device offset
trim.
0x14 Output mode Open LVDS-ANSI/
LVDS-IEEE
option
0 = LVDS-ANSI
1 = LVDS-IEEE
reduced range
link (global);
see
Table 17
Open Open Open Output
invert
(local)
Open Output
format
0 = offset
binary
1 = twos
comple-
ment
(global)
0x01 Configures
the outputs
and format of
the data.
0x15 Output adjust Open Open Output driver
termination, Bits[1:0]
00 = none
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
Open Open Open Output
drive
0 = 1×
drive
1 = 2×
drive
0x00 Determines
LVDS or other
output
properties.
0x16 Output phase Open Input clock phase adjust, Bits[6:4]
(value is number of input clock cycles
of phase delay); see
Table 18
Output clock phase adjust, Bits[3:0]
(0000 through 1011); see
Table 19
0x03 On devices
using global
clock divide,
determines
which phase
of the divider
output is used
to supply the
output clock.
Internal
latching is
unaffected.
0x18 V
REF
Open Open Open Open Open Internal V
REF
adjustment
digital scheme, Bits[2:0]
000 = 1.0 V p-p
001 = 1.14 V p-p
010 = 1.33 V p-p
011 = 1.6 V p-p
100 = 2.0 V p-p
0x04 Selects and/or
adjusts V
REF
.
0x19 USER_PATT1_LSB
(global)
B7 B6 B5 B4 B3 B2 B1 B0 0x00 User Defined
Pattern 1 LSB.
0x1A USER_PATT1_MSB
(global)
B15 B14 B13 B12 B11 B10 B9 B8 0x00 User Defined
Pattern 1 MSB.
0x1B
USER_PATT2_LSB
(global)
B7
B6
B5
B4
B3
B2
B1
B0
0x00
User Defined
Pattern 2 LSB.
0x1C USER_PATT2_MSB
(global)
B15 B14 B13 B12 B11 B10 B9 B8 0x00 User Defined
Pattern 2 MSB.