Datasheet

Data Sheet AD9645
Rev. 0 | Page 27 of 36
SERIAL PORT INTERFACE (SPI)
The AD9645 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI
offers the user added flexibility and customization, depending on
the application. Addresses are accessed via the serial port and
can be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, which are docu-
mented in the Memory Map section. For detailed operational
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK/DFS pin,
the SDIO/PDWN pin, and the CSB pin (see Table 14). SCLK/DFS
(a serial clock when CSB is low) is used to synchronize the read
and write data presented from and to the ADC. SDIO/PDWN
(serial data input/output when CSB is low) is a dual-purpose
pin that allows data to be sent to and read from the internal ADC
memory map registers. CSB (chip select bar) is an active low
control that enables or disables the SPI read and write cycles.
Table 14. Serial Port Interface Pins
Pin Function
SCLK/DFS Serial clock when CSB is low. The serial shift clock
input, which is used to synchronize serial interface
reads and writes.
SDIO/PDWN Serial data input/output when CSB is low. A dual-
purpose pin that typically serves as an input or an
output, depending on the instruction being sent
and the relative position in the timing frame.
CSB Chip select bar. An active low control that enables
the SPI mode read and write cycles.
The falling edge of CSB, in conjunction with the rising edge of
SCLK/DFS, determines the start of the framing. An example of
the serial timing is shown in Figure 68. See Table 5 for definitions
of the timing parameters.
Other modes involving the CSB pin are available. CSB can be
held low indefinitely, which permanently enables the device; this
is called streaming. CSB can stall high between bytes to allow
for additional external timing. When the CSB pin is tied high,
SPI functions are placed in high impedance mode. This mode
turns on the secondary functions of the SPI pins.
During the instruction phase of a SPI operation, a 16-bit
instruction is transmitted. Data follows the instruction phase,
and its length is determined by the W0 and W1 bits.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. The first bit of the first byte
in a multibyte serial data transfer frame indicates whether a read
command or a write command is issued. If the instruction is a
readback operation, performing a readback causes the serial
data input/output (SDIO) pin to change direction from an input
to an output at the appropriate point in the serial frame.
All data is composed of 8-bit words. Data can be sent in MSB-
first mode or in LSB-first mode. MSB-first mode is the default
on power-up and can be changed via the SPI port configuration
register. For more information about this and other features,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.
DON’T CARE
DON’T CAREDON’T CARE
DON’T CARE
SDIO
SCLK
CSB
t
S
t
DH
t
CLK
t
DS
t
H
R/W W1 W0 A12 A11 A10 A9 A8 A7
D5 D4 D3 D2 D1 D0
t
LOW
t
HIGH
10537-062
Figure 68. Serial Port Interface Timing Diagram