Datasheet

AD9645 Data Sheet
Rev. 0 | Page 26 of 36
SDIO/PDWN Pin
For applications that do not require SPI mode operation, the
CSB pin is tied to DRVDD, and the SDIO/PDWN pin controls
power-down mode according to Table 12.
Table 12. Power-Down Mode Pin Settings
PDWN Pin Voltage Device Mode
AGND (Default) Run device, normal operation
DRVDD Power down device
Note that in non-SPI mode (CSB tied to DRVDD), the power-
up sequence described in the Power and Ground Guidelines
section must be adhered to. Violating the power-up sequence
necessitates a soft reset via the SPI, which is not possible in
non-SPI mode.
SCLK/DFS Pin
The SCLK/DFS pin is used for output format selection in
applications that do not require SPI mode operation. This pin
determines the digital output format when the CSB pin is held
high during device power-up. When SCLK/DFS is tied to DRVDD,
the ADC output format is twos complement; when SCLK/DFS
is tied to AGND, the ADC output format is offset binary.
Table 13. Digital Output Format
DFS Voltage Output Format
AGND Offset binary
DRVDD Twos complement
CSB Pin
The CSB pin should be tied to DRVDD for applications that do
not require SPI mode operation. By tying CSB high, all SCLK
and SDIO information is ignored.
Note that, in non-SPI mode (CSB tied to DRVDD), the power-up
sequence described in the Power and Ground Guidelines
section must be adhered to. Violating the power-up sequence
necessitates a soft reset via SPI, which is not possible in non-SPI
mode.
RBIAS Pin
To set the internal core bias current of the ADC, place a 10.0 kΩ,
1% tolerance resistor to ground at the RBIAS pin.
OUTPUT TEST MODES
The output test options are described in Table 10 and are
controlled by the output test mode bits at Address 0x0D. When an
output test mode is enabled, the analog section of the ADC is
disconnected from the digital back-end blocks and the test pattern
is run through the output formatting block. Some of the test
patterns are subject to output formatting, and some are not. The
PN generators from the PN sequence tests can be reset by
setting Bit 4 or Bit 5 of Register 0x0D. These tests can be
performed with or without an analog signal (if present, the
analog signal is ignored), but they do require an encode clock.
For more information, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.