Datasheet

Data Sheet AD9645
Rev. 0 | Page 25 of 36
Table 10. Flexible Output Test Modes
Output Test
Mode Bit
Sequence
Pattern Name Digital Output Word 1 Digital Output Word 2
Subject to
Data Format
Select
Notes
0000
Off (default)
N/A
N/A
N/A
0001 Midscale short 1000 0000 0000 (12-bit)
1000 0000 0000 0000 (16-bit)
N/A Yes Offset binary
code shown
0010 +Full-scale short 1111 1111 1111 (12-bit)
0000 0000 0000 0000 (16-bit)
N/A Yes Offset binary
code shown
0011 −Full-scale short 0000 0000 0000 (12-bit)
0000 0000 0000 0000 (16-bit)
N/A Yes Offset binary
code shown
0100 Checkerboard 1010 1010 1010 (12-bit)
1010 1010 1010 1010 (16-bit)
0101 0101 0101 (12-bit)
0101 0101 0101 0100 (16-bit)
No
0101 PN sequence long
1
N/A N/A Yes PN23
ITU 0.150
X
23
+ X
18
+ 1
0110 PN sequence short
1
N/A N/A Yes PN9
ITU 0.150
X
9
+ X
5
+ 1
0111 One-/zero-word
toggle
1111 1111 1111 (12-bit)
111 1111 1111 1100 (16-bit)
0000 0000 0000 (12-bit)
0000 0000 0000 0000 (16-bit)
No
1000 User input Register 0x19 and Register 0x1A Register 0x1B and Register 0x1C No
1001 1-/0-bit toggle 1010 1010 1010 (12-bit)
1010 1010 1010 1000 (16-bit)
N/A No
1010 1× sync 0000 0011 1111 (12-bit)
0000 0001 1111 1100 (16-bit)
N/A No
1011
One bit high
1000 0000 0000 (12-bit)
1000 0000 0000 0000 (16-bit)
N/A
No
Pattern
associated
with the
external pin
1100 Mixed frequency 1010 0011 0011 (12-bit)
1010 0001 1001 1100 (16-bit)
N/A No
1
All test mode options except PN sequence short and PN sequence long can support 12-bit to 16-bit word lengths to verify data capture to the receiver.
There are 12 digital output test pattern options available that
can be initiated through the SPI. This is a useful feature when
validating receiver capture and timing. Refer to Table 10 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various ways,
depending on the test pattern chosen.
Note that some patterns do not adhere to the data format select
option. In addition, custom user-defined test patterns can be
assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses.
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 2
9
− 1 or 511 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The
seed value is all 1s (see Table 11 for the initial values). The output
is a parallel representation of the serial PN9 sequence in MSB-first
format. The first output word is the first 14 bits of the PN9
sequence in MSB aligned form.
Table 11. PN Sequence
Sequence
Initial
Value
First Three Output Samples
(MSB First), Twos Complement
PN Sequence Short 0x1FE0 0x1DF1, 0x3CC8, 0x294E
PN Sequence Long 0x1FFF 0x1FE0, 0x2001, 0x1C00
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 2
23
− 1 or 8,388,607 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
seed value is all 1s (see Table 11 for the initial values) and the
AD9645 inverts the bit stream with relation to the ITU standard.
The output is a parallel representation of the serial PN23 sequence
in MSB-first format. The first output word is the first 14 bits of the
PN23 sequence in MSB aligned form.
Consult the Memory Map section for information on how to
change these additional digital output timing features through
the SPI.