Datasheet

AD9645 Data Sheet
Rev. 0 | Page 24 of 36
Figure 67 shows an example of trace lengths exceeding 24 inches
on standard FR-4 material. Note that the TIE jitter histogram
reflects the decrease of the data eye opening as the edge deviates
from the ideal position.
500
400
300
200
100
–500
–400
–300
–200
–100
0
–0.8ns –0.4ns
0ns 0.4ns 0.8ns
EYE DIAGRAM VOLTAGE (mV)
EYE: ALL BITS ULS: 8000/414024
10k
12k
2k
4k
6k
8k
0
–800ps –600ps –400ps –200ps 0ps 200ps 400ps 600ps
TIE JITTER HISTOGRAM (Hits)
10537-061
Figure 67. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater Than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End
Termination Only
It is the responsibility of the user to determine if the waveforms
meet the timing budget of the design when the trace lengths exceed
24 inches. Additional SPI options allow the user to further increase
the internal termination (increasing the current) of both outputs
to drive longer trace lengths. This increase in current can be
achieved by programming Register 0x15. Although an increase
in current produces sharper rise and fall times on the data edges
and is less prone to bit errors, the power dissipation of the DRVDD
supply increases when this option is used.
The format of the output data is twos complement by default.
An example of the output coding format can be found in Table 9.
To change the output data format to offset binary, see the
Memory Map section.
Data from each ADC is serialized and provided on a separate
channel in two lanes in DDR mode. The data rate for each serial
stream is equal to (16 bits × the sample clock rate)/2 lanes, with
a maximum of 1 Gbps/lane [(16 bits × 125 MSPS)/(2 lanes) =
1 Gbps/lane)]. The lowest typical conversion rate is 10 MSPS.
For conversion rates of less than 20 MSPS, the SPI must be used
to reconfigure the integrated PLL. See Register 0x21 in the
Memory Map section for details on enabling this feature.
Two output clocks are provided to assist in capturing data from
the AD9645. The DCO is used to clock the output data and is
equal to 4× the sample clock (CLK) rate for the default mode
of operation. Data is clocked out of the AD9645 and must be
captured on the rising and falling edges of the DCO that supports
double data rate (DDR) capturing. The FCO is used to signal
the start of a new output byte and is equal to the sample clock
rate in 1× frame mode. See the Timing Diagrams section for
more information.
When the SPI is used, the DCO phase can be adjusted in 60°
increments relative to the data edge. This enables the user to
refine system timing margins, if required. The default DCO+
and DCO− timing, as shown in Figure 2, is 180° relative to the
output data edge.
A 12-bit serial stream can also be initiated from the SPI. This
allows the user to implement and test compatibility to lower
resolution systems. When changing the resolution to a 12-bit
serial stream, the data stream is shortened. See Figure 3 for the
12-bit example. In the default option with the serial output
number of bits at 16, the data stream stuffs two 0s at the end of
the 14-bit serial data.
In default mode, as shown in Figure 2, the MSB is first in the
data output serial stream. This can be inverted by using the SPI
so that the LSB is first in the data output serial stream.
Table 9. Digital Output Coding
Input (V) Condition (V) Offset Binary Output Mode Twos Complement Mode
VIN+ − VIN− <−VREF − 0.5 LSB 0000 0000 0000 0000 1000 0000 0000 0000
VIN+ − VIN− −VREF 0000 0000 0000 0000 1000 0000 0000 0000
VIN+ − VIN− 0 V 1000 0000 0000 0000 0000 0000 0000 0000
VIN+ − VIN− +VREF − 1.0 LSB 1111 1111 1111 1100 0111 1111 1111 1100
VIN+ − VIN− >+VREF − 0.5 LSB 1111 1111 1111 1100 0111 1111 1111 1100