Datasheet

Data Sheet AD9645
Rev. 0 | Page 23 of 36
DIGITAL OUTPUTS AND TIMING
The AD9645 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This default setting can be changed
to a low power, reduced signal option (similar to the IEEE 1596.3
standard) via the SPI. The LVDS driver current is derived on chip
and sets the output current at each output equal to a nominal
3.5 mA. A 100 Ω differential termination resistor placed at the
LVDS receiver inputs results in a nominal 350 mV swing (or
700 mV p-p differential) at the receiver.
When operating in reduced range mode, the output current is
reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-p
differential) across a 100 Ω termination at the receiver.
The LVDS outputs facilitate interfacing with LVDS receivers in
custom ASICs and FPGAs for superior switching performance
in noisy environments. Single point-to-point net topologies are
recommended with a 100 Ω termination resistor placed as close
as possible to the receiver. If there is no far-end receiver termi-
nation or there is poor differential trace routing, timing errors
may result. To avoid such timing errors, ensure that the trace
length is less than 24 inches and that the differential output traces
are close together and at equal lengths.
Figure 64 shows an example of the FCO and data stream with
proper trace length and position.
D0 500mV/DIV
D1 500mV/DIV
DCO 500mV/DIV
FCO 500mV/DIV
4ns/DIV
10537-058
Figure 64. AD9645-125, LVDS Output Timing Example in ANSI-644 Mode (Default)
Figure 65 shows the LVDS output timing example in reduced
range mode.
D0 400mV/DIV
D1 400mV/DIV
DCO 400mV/DIV
FCO 400mV/DIV
4ns/DIV
10537-059
Figure 65. AD9645-125, LVDS Output Timing Example in Reduced Range Mode
Figure 66 shows an example of the LVDS output using the
ANSI-644 standard (default) data eye and a time interval error
(TIE) jitter histogram with trace lengths of less than 24 inches
on standard FR-4 material.
6k
7k
1k
2k
3k
5k
4k
0
200ps 250ps 300ps 350ps 400ps 450ps 500ps
TIE JITTER HISTOGRAM (Hits)
500
400
300
200
100
–500
–400
–300
–200
–100
0
–0.8ns –0.4ns 0ns 0.4ns 0.8ns
EYE DIAGRAM VOLTAGE (mV)
EYE: ALL BITS
ULS: 7000/400354
10537-060
Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
of Less Than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End
Termination Only