Datasheet

AD9645 Data Sheet
Rev. 0 | Page 22 of 36
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a variety
of internal timing signals and, as a result, may be sensitive to the
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9645 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide
a wide range of clock input duty cycles without affecting the perfor-
mance of the AD9645. Noise and distortion performance are nearly
flat for a wide range of duty cycles with the DCS on.
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates of less than 20 MHz,
nominally. The loop has a time constant associated with it that
must be considered in applications in which the clock rate can
change dynamically. A wait time of 1.5 µs to 5 µs is required after
a dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input signal.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(f
A
) due only to aperture jitter (t
J
) can be calculated by the
following equation:
SNR Degradation = 20 log
10








××
J
A
tf π 2
1
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 62).
1 10 100 1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
SNR (dB)
10537-056
Figure 62. Ideal SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases where
aperture jitter may affect the dynamic range of the AD9645. Power
supplies for clock drivers should be separated from the ADC
output driver supplies to avoid modulating the clock signal with
digital noise. Low jitter, crystal-controlled oscillators make the
best clock sources. If the clock is generated from another type of
source (by gating, dividing, or other methods), it should be
retimed by the original clock as the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
POWER DISSIPATION AND POWER-DOWN MODE
As shown in Figure 63, the power dissipated by the AD9645 is
proportional to its sample rate. The AD9645 is placed in power-
down mode either by the SPI port or by asserting the PDWN
pin high. In this state, the ADC typically dissipates 2 mW. During
power-down, the output drivers are placed in a high impedance
state. Asserting the PDWN pin low returns the AD9645 to its
normal operating mode. Note that PDWN is referenced to the
digital output driver supply (DRVDD) and should not exceed
that supply voltage.
240
180
200
220
160
140
120
100
10 130
TOTAL POWER DISSIPATION (mW)
SAMPLE RATE (MSPS)
30 50 70 90 110
50MSPS
80MSPS
125MSPS
40MSPS
20MSPS
65MSPS
105MSPS
10537-079
Figure 63. Total Power Dissipation vs. f
SAMPLE
for f
IN
= 9.7 MHz
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when the part enters
power-down mode and must then be recharged when the part
returns to normal operation. As a result, wake-up time is related
to the time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times. When using
the SPI port interface, the user can place the ADC in power-down
mode or standby mode. Standby mode allows the user to keep
the internal reference circuitry powered when faster wake-up
times are required. See the Memory Map section for more
details on using these features.