Datasheet

Data Sheet AD9645
Rev. 0 | Page 19 of 36
THEORY OF OPERATION
The AD9645 is a multistage, pipelined ADC. Each stage
provides sufficient overlap to correct for flash errors in the
preceding stage. The quantized outputs from each stage are
combined into a final 14-bit result in the digital correction
logic. The serializer transmits this converted data in a 16-bit
output. The pipelined architecture permits the first stage to
operate with a new input sample while the remaining stages
operate with preceding samples. Sampling occurs on the rising
edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and data clocks.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9645 is a differential switched-
capacitor circuit designed for processing differential input
signals. This circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.
S S
H
C
PAR
C
SAMPLE
C
SAMPLE
C
PAR
VINx–
H
S S
H
VINx+
H
10537-044
Figure 51. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 51). When the input
circuit is switched to sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle.
A small resistor in series with each input can help reduce the
peak transient current injected from the output stage of the
driving source. In addition, low Q inductors or ferrite beads can
be placed on each leg of the input to reduce high differential
capacitance at the analog inputs and, therefore, achieve the
maximum bandwidth of the ADC. Such use of low Q inductors
or ferrite beads is required when driving the converter front end at
high IF frequencies. Either a differential capacitor or two single-
ended capacitors can be placed on the inputs to provide a
matching passive network. This ultimately creates a low-pass
filter at the input to limit unwanted broadband noise. See the
AN-742 Application Note, the AN-827 Application Note, and the
Analog Dialogue article “Transformer-Coupled Front-End for
Wideband A/D Converters” (Volume 39, April 2005) for more
information. In general, the precise values depend on the
application.
Input Common Mode
The analog inputs of the AD9645 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide
this bias externally. Setting the device so that V
CM
= AVDD/2 is
recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 52.
100
20
0.5 1.3
SNR/SFDR (dBFS/dBc)
INPUT COMMON MODE (V)
30
40
50
60
70
80
90
0.6 0.7 0.8 0.9 1.0 1.1 1.2
SFDR
SNRFS
10537-078
Figure 52. SNR/SFDR vs. Input Common-Mode Voltage,
f
IN
= 9.7 MHz, f
SAMPLE
= 125 MSPS
An on-chip, common-mode voltage reference is included in the
design and is available from the VCM pin. The VCM pin must
be decoupled to ground by a 0.1 µF capacitor, as described in
the Applications Information section.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9645, the largest input span available is 2 V p-p.