Datasheet

Evaluation Board User Guide UG-294
Rev. B | Page 7 of 48
JESD204A Output Modes
The AD9641 evaluation platform supports one JESD204A output mode (see Table 1), and the AD9644 evaluation platform supports
several JESD204A output modes (see Table 2 for typical configurations). Each mode requires a different FPGA configuration to capture
data properly. Output Configuration A in Table 2 is the configuration for the default mode for the AD9644, and it consists of two
converters, each of which has two links and one output lane.
Table 1. AD9641 JESD204A Configuration
Output
Configuration
AD9641
Configuration
JESD204A
Link Settings Comments
A
One converter,
One JESD204A link,
One lane per link
M = 1; L = 1; S = 1; F = 2;
N’ = 16; CF = 0; CS = 0, 1, 2;
K = N/A; SCR = 0, 1; HD = 0
Maximum sample rate =
80 MSPS or 155 MSPS
Table 2. AD9644 JESD204A Typical Configurations (Enabled Through SPI Register 0x5E, Bits[2:0])
Output
Configuration
AD9644
Configuration
JESD204A
Link A Settings
JESD204A
Link B Settings
Comments
A
Two converters,
two JESD204A links,
one lane per link
M = 1; L = 1; S = 1; F = 2;
N’ = 16; CF = 0; CS = 0, 1, 2;
K = N/A; SCR = 0, 1; HD = 0
M = 1; L = 1; S = 1; F = 2;
N’ = 16; CF = 0; CS = 0, 1, 2;
K = N/A; SCR = 0, 1; HD = 0
Maximum sample rate =
80 MSPS
B
Two converters,
one JESD204A link,
two lanes per link
M = 2; L = 2; S = 1; F = 2;
N’ = 16; CF = 0; CS = 0, 1, 2;
K = see the specifications
in the AD9644 data sheet;
SCR = 0, 1; HD = 0
Disabled
Maximum sample rate =
80 MSPS
This configuration is required for
applications needing two
aligned samples (that is, I/Q
applications)
C
Two converters,
one JESD204A link,
one lane per link
M = 2; L = 1; S = 1; F = 4;
N’ = 16; CF = 0; CS = 0, 1, 2;
K = see the specifications
in the AD9644 data sheet;
SCR = 0, 1; HD = 0
Disabled
Maximum sample rate =
80 MSPS