Datasheet

UG-294 Evaluation Board User Guide
Rev. B | Page 12 of 48
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Figure 12. SPI Controller, Example ADC A Tab
7. If Configuration B (two converters, one JESD204A link, two
lanes per link) is selected, click the FACI Disable check box
in the JTX LINK CTRL1 box (shown in Figure 13) for both
Channel A and Channel B (ADC A and ADC B tabs) for
the AD9644, or for only Channel A (ADC A tab) for the
AD9641. Changing this selection sets the part to match the
expected FPGA input configuration.
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Figure 13. SPI Controller, Example ADC A Tab
8. Click the Run button in the VisualAnalog toolbar (see
Figure 14).
RUN BUTTON
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Figure 14. Run Button in VisualAnalog Toolbar, Collapsed Display
Adjusting the Amplitude of the Input Signal
Next, adjust the amplitude of the input signal for each channel
as follows:
1. Adjust the amplitude of the input signal for Channel A so
that the fundamental is at the desired level. (Examine the
Fund Power reading in the left panel of the VisualAnalog
Graph – AD9644 Average FFT window (see Figure 15).)
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Figure 15. Graph Window of VisualAnalog
2. Repeat Step 1 for Channel B on the AD9644.
3. Click the disk icon within the graph for Channel A to save the
performance plot data as a .csv formatted file. See Figure 16
for an example.
0
–20
–40
–60
–80
–100
–120
–140
0 10 20
30 40
AMPLITUDE (dBFS)
FREQUENCY (MHz)
80MSPS
10.1MHz @ –1dBFS
SNR = 73.0dB (74.0dBFS)
SFDR = 95dBc
THIRD HARMONIC
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Figure 16. Typical FFT, AD9644
4. Repeat Step 3 for Channel B on the AD9644.