Datasheet
UG-294 Evaluation Board User Guide
Rev. B | Page 30 of 48
LAYOUT : SHARE PADS WIT H ACTIVE CLOC K PATH R'S
LAYOUT : SMA' S SHOUL D BE 540 MIL S CENTER TO CENTER
REF
CLK
CLK
PECL/CML/LVD S CLK CIRCUITRY
KP_ICELL
1
4
8
7
2
U503
R554
R553
R552
R551
R550
R549
R527
R526
R525
R524
2
1
E502
L506
1
TP505
1
TP504
R521
R520
R523
R522
2
1
E501
C527
C534
C526
C525
C524
L501
L502
L503
L504
L505
R501
R510
C516
C514
R511
C520
C521
R512
R518
3
2
1
J501
R517
R515
R516
C515
1
TP501
C513
44
43
24
34
42
11
14
21
31
39
48
13
35
36
18
17
16
26
4
3
2
1
25
45
46
27
PAD
19
20
22
23
29
30
32
33
37
38
40
41
8
7
6
9
5
12
10
47
28
15
U501
R519
R509
C508
C511
C510
R507
C509
C512
R508
A C
CR501
A C
CR502
C504
C507
R505
R503R604
R502
C503
C506
R506
R513
R514
C519
4
6
5
2
3
1
U300
6
1
5
4
3
Y501
C505
1
TP502
1
TP503
R547
R548
R532
R531
C531
R544R545
C530
R542
R541
R533R534
C532
R539
R543
C533
1
2
3
CR503
C528
R540
5
4 3
1
T503
R537
C522
R528
R529
5432
1
J505
C529
6
4
2
3
1
T502
R538
C523
R530
5432
1
J506
5 4 3 2
1
J503C518
5 4 3 2
1
J502C517
C502
C501
1.8V_OUT_0-5
1.8V_OUT_0-5
1.8V_OUT_0-5
OUT3_N
OUT0_N
OUT0
3.3V_PLL1
RESETB
PDB
EEPROM_SEL
OUT3
3.3V_OUT_2-5
OUT2_N
OUT2
STATUS1/SP1
STATUS0/SP0
OUT4
OUT4_N
3.3V_OUT_2-5
CYP_SDO
CYP_SDI
CYP_SCLK
USB_CSB2
3.3V_REF
SYNCB
3.3V_PLL2
AD9524_PRELIM
3P3V_ANALOG
FIN1017M
0.1UF
CLK_IN+
0.1UF
0.1UF
0.1UF
CLK_OUT+
0.1UF
CLK_OUT-
0.1UF
10UF
10UF
10UF
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
3.3V_OUT_0-1
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
DNI
0.1UF
0.1UF
DNI
0.1UF
O4N
0.1UF
O4
0.1UF
CLK_IN-
0.1UF
CLK_IN+
0.1UF
0.47UF
0.47UF
DNI
DNI
DNI
DNI
DNI
DNI
0
DNI
DNI
DNI
TBD0402
OUT3_N
OUT3
10K 10K
60-800MHZ
0
REFCLK1-
0
DNI
DNI
DNI
DNI
REFCLK-
REFCLK2X+
REFCLK2X-
+1KLCFER+KLCFER
REFCLK2-
REFCLK2+
0
REFCLK-
0
0
0
REFCLK+
0
0
0
0
ETC1-1-13
0
3.3V_REF
3.3V_PLL2
1UH
3.3V_PLL1
3.3V_OUT_0-1
3.3V_OUT_2-5
1UH
1UH
CLK-
CLK+
KP_ICELL
100
24.9
DNI
DNI
0
DNI
DNI
0
0
DNI
0
0
200
100
DNI
10K10K
NC7WZ16P6X
10K
10K
100
100
10K
0.33UF
49.9
1K
49.9
49.9
0
0.33UF
3.3V_OUT_2-5
OUT0_N
3.3V_REF
3.3V_PLL1
OUT2_N
OUT2
OUT0
SI04
3.3V_REF
0
3.3V_OUT_2-5
VCXO_CTRL
49.9
DNI
ADT1-1WT+
0
DNI
0
DNI
0
DNI
0
CLK_IN-
10K
200
200
DNI
DNI
1UH
1UH
DRVDD
1.8V_OUT_0-5
45OHMS
3P3V_ANALOG
45OHMS
49.9
0
DNI
24.9
CLK_OUT+
1UH
3P3V_DIGITAL
49.9
3.3V_OUT_0-1
DNI
200
OUT4
OUT4_N
0
CLK_OUT-
DNI
0.001UF
0.001UF
DOUT-
DOUT+
GND
DIN
VCC
AGND
AGND
AGND
AGND
AGND
AGND
VDD_1_8_OUT_0_1
VDD_1_8_OUT_2_3
VDD_1_8_OUT_4_5
OUT1_N
OUT 3_N
OUT1
VDD3_OUT_0_1
OUT0_N
OUT0
ZD_IN
ZD_IN_N
REF_SEL
PLL1_OUT
LDO_PLL1
VDD3_CP
PAD
REF_TEST
RESET_N
PD_N
EEPROM_SEL
OUT3
VDD3_OUT_2_3
OUT 2_N
OUT2
STATUS_1_I2C_SP1
STATUS_0_I2C_SP0
OUT4
OUT4_N
VDD3_OUT_4_5
OUT5
OUT5_N
SDO
SDIO
SCLK_SCL
CS_N_SDA
VDD3_REF
SYNC_N
LDO_VCO
VDD3_VCO
LDO_PLL2
LF2_EXT_CAP
OSC_IN_N
OSC_IN
OSC_CTRL
LF1_EXT_CAP
REFB_N
REFB
REFA_N
REFA AGND
AGND
AGND
AGND
AGND
Y2
Y1
A2
A1
GND
VCC
OUT-
OUT+
VC
VCC
GND
AGND
AGND
AGND
AGND
SEC
PRI
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
09941-033
Figure 33. AD9641 Clock Input Circuits