Datasheet

UG-294 Evaluation Board User Guide
Rev. B | Page 10 of 48
4. If the input clock divider is used or if testing in Configura-
tion C is desired, a nonstandard FPGA configuration file is
required. To program the FPGA with a nonstandard con-
figuration, click ADC Data Capture, and the ADC Data
Capture Settings window appears. Click the Capture
Board tab. Under the FPGA area, select the appropriate
FPGA configuration file from the Program Files: box (see
Table 2 and Figure 8). The selected FPGA configuration is
then downloaded to the hardware using VisualAnalog.
Table 2 details the configurations that are available to
program the FPGA.
Table 3. AD9644 and AD9641 JESD204A Typical Configurations
Output Configuration
AD9644 AD9641 Clock Divider FPGA Configuration File Name
A and B A Disabled (Default) ad9644_41.rbf (default)
A and B A Set to Divide by 2 ad9644_41_div2.rbf
A and B A Set to Divide by 3 ad9644_41_div3.rbf
A and B A Set to Divide by 4 ad9644_41_div4.rbf
A and B A Set to Divide by 5 ad9644_41_div5.rbf
A and B
A
Set to Divide by 6
ad9644_41_div6.rbf
A and B A Set to Divide by 7 ad9644_41_div7.rbf
A and B A Set to Divide by 8 ad9644_41_div8.rbf
C A Disabled ad9644_41_config3.rbf
09941-008
Figure 8. VisualAnalog, Main Window, Data Capture Settings