Datasheet

Data Sheet AD9637
Rev. A | Page 7 of 40
Timing Diagrams
DCO–
DCO+
D– x
D+ x
FCO–
FCO+
CLK–
CLK+
MSB
N – 17
D10
N – 17
D9
N – 17
D8
N – 17
D7
N – 17
D6
N – 17
D5
N – 17
D4
N – 17
D3
N – 17
D2
N – 17
D1
N – 17
D0
N – 17
D10
N – 16
MSB
N – 16
N – 1
N
t
DATA
t
FRAME
t
FCO
t
PD
t
CPD
t
EH
t
A
t
EL
05967-002
VIN± x
Figure 2. Word-Wise DDR, 1× Frame, 12-Bit Output Mode (Default)
10215-003
DCO+
DCO–
CLK+
FCO+
FCO–
D– x
D+ x
CLK–
MSB
N – 17
N – 1
N
D8
N – 17
D7
N – 17
D5
N – 17
t
DATA
t
FRAME
t
FCO
t
PD
D4
N – 17
D6
N – 17
D8
N – 16
D7
N – 16
D5
N – 16
D6
N – 16
D3
N – 17
D1
N – 17
MSB
N – 16
D0
N – 17
D2
N – 17
t
CPD
t
EH
t
A
t
EL
VIN± x
Figure 3. Word-Wise DDR, 1× Frame, 10-Bit Output Mode
SYNC
CLK+
t
HSYNC
t
SSYNC
10215-004
Figure 4. SYNC Input Timing Requirements