Datasheet

Data Sheet AD9637
Rev. A | Page 35 of 40
Output Phase (Register 0x16)
Bit 7—Open
Bits[6:4]—Input Clock Phase Adjust
When the clock divider (Register 0x0B) is used, the applied
clock is at a higher frequency than the internal sampling
clock. Bits[6:4] determine at which phase of the external
clock sampling occurs. This is only applicable when the
clock divider is used. Selecting Bits[6:4] greater than
Register 0x0B Bits[2:0] is prohibited.
Table 19. Input Clock Phase Adjust Options
Input Clock Phase
Adjust, Bits[6:4]
Number of Input Clock Cycles of
Phase Delay
000 (Default) 0
001 1
010 2
011 3
100
4
101 5
110 6
111 7
Bits[3:0]—Output Clock Phase Adjust
Table 20. Output Clock Phase Adjust Options
Output Clock (DCO),
Phase Adjust, Bits[3:0]
DCO Phase Adjustment
(Degrees Relative to D± x Edge)
0000 0
0001 60
0010 120
0011 (Default) 180
0100 240
0101 300
0110 360
0111
420
1000 480
1001 540
1010 600
1011 660
Resolution/Sample Rate Override (Register 0x100)
This register is designed to allow the user to downgrade the device.
Any attempt to upgrade the default speed grade results in a chip
power-down. Settings in this register are not initialized until Bit 0
of the transfer register (Register 0xFF) is written high.
User I/O Control 2 (Register 0x101)
Bits[7:1]—Open
Bit 0—SDIO Pull-Down
Bit 0 can be set to disable the internal 30 kΩ pull-down on the
SDIO pin, which can be used to limit loading when many
devices are connected to the SPI bus.
User I/O Control 3 (Register 0x102)
Bits[7:4]—Open
Bit 3—VCM Power-Down
Bit 3 can be set high to power down the internal VCM generator.
This feature is used when applying an external reference.
Bits[2:0]—Open