Datasheet

Data Sheet AD9637
Rev. A | Page 23 of 40
DIGITAL OUTPUTS AND TIMING
The AD9637 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option (similar to the IEEE 1596.3 standard) via the
SPI. The LVDS driver current is derived on chip and sets the
output current at each output equal to a nominal 3.5 mA. A 100 Ω
differential termination resistor placed at the LVDS receiver
inputs results in a nominal 350 mV swing (or 700 mV p-p
differential) at the receiver.
When operating in reduced range mode, the output current is
reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-p
differential) across a 100 Ω termination at the receiver.
The AD9637 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is
recommended that the trace length be less than 24 inches and
that the differential output traces be close together and at equal
lengths. An example of the FCO and data stream with proper
trace length and position is shown in Figure 57. An example of
LVDS output timing in reduced range mode is shown in Figure 58.
10215-056
FCO 500mV/DIV
DCO 500mV/DIV
DATA 500mV/DIV
5ns/DIV
Figure 57. LVDS Output Timing Example in ANSI-644 Mode (Default)
10215-057
FCO 500mV/DIV
DCO 500mV/DIV
DATA 500mV/DIV
5ns/DIV
Figure 58. LVDS Output Timing Example in Reduced Range Mode