Datasheet

AD9634
Rev. 0 | Page 8 of 32
TIMING SPECIFICATIONS
Table 5.
Parameter Test Conditions/Comments Min Typ Max Unit
SPI TIMING REQUIREMENTS See Figure 58 for the SPI timing diagram
t
DS
Setup time between the data and the rising edge of SCLK 2 ns
t
DH
Hold time between the data and the rising edge of SCLK 2 ns
t
CLK
Period of the SCLK 40 ns
t
S
Setup time between CSB and SCLK 2 ns
t
H
Hold time between CSB and SCLK 2 ns
t
HIGH
Minimum period that SCLK should be in a logic high state 10 ns
t
LOW
Minimum period that SCLK should be in a logic low state 10 ns
t
EN_SDIO
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge (not shown in Figure 58)
10 ns
t
DIS_SDIO
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge (not shown in Figure 58)
10 ns