Datasheet

AD9634
Rev. 0 | Page 7 of 32
SWITCHING SPECIFICATIONS
Table 4.
AD9634-170 AD9634-210 AD9634-250
Parameter Temperature Min Typ Max Min Typ Max Min Typ Max Unit
CLOCK INPUT PARAMETERS
1
Input Clock Rate Full 625 625 625 MHz
Conversion Rate
2
DCS Enabled Full 40 170 40 210 40 250 MSPS
DCS Disabled Full 10 170 10 210 10 250 MSPS
CLK Period, Divide-by-1 Mode (t
CLK
) Full 5.8 4.8 4 ns
CLK Pulse Width High (t
CH
)
Divide-by-1 Mode, DCS Enabled Full 2.61 2.9 3.19 2.16 2.4 2.64 1.8 2.0 2.2 ns
Divide-by-1 Mode, DCS Disabled Full 2.76 2.9 3.05 2.28 2.4 2.52 1.9 2.0 2.1 ns
Divide-by-2 Mode Through
Divide-by-8 Mode
Full 0.8 0.8 0.8 ns
Aperture Delay (t
A
) Full 1.0 1.0 1.0 ns
Aperture Uncertainty (Jitter, t
J
) Full 0.1 0.1 0.1 ps rms
DATA OUTPUT PARAMETERS
1
Data Propagation Delay (t
PD
) Full 4.1 4.7 5.2 4.1 4.7 5.2 4.1 4.7 5.2 ns
DCO Propagation Delay (t
DCO
) Full 4.7 5.3 5.8 4.7 5.3 5.8 4.7 5.3 5.8 ns
DCO to Data Skew (t
SKEW
) Full 0.3 0.5 0.7 0.3 0.5 0.7 0.3 0.5 0.7 ns
Pipeline Delay (Latency) Full 10 10 10 Cycles
Wake-Up Time (from Standby) Full 10 10 10 μs
Wake-Up Time (from Power-Down) Full 100 100 100 μs
Out-of-Range Recovery Time Full 3 3 3 Cycles
1
See . Figure 2
2
Conversion rate is the clock rate after the divider.
Timing Diagram
VIN
CLK+
CLK–
DCO–
DCO+
D0±/D1±
(LSB)
EVEN/ODD
D10±/D11±
(MSB)
D0
N – 10
D1
N – 10
D0
N – 9
D1
N – 9
D0
N – 8
D1
N – 8
D0
N – 7
D1
N – 7
D0
N – 6
D10
N – 10
D11
N – 10
D10
N – 9
D11
N – 9
D10
N – 8
D11
N – 8
D10
N – 7
D11
N – 7
D10
N – 6
N – 1
N
N + 1
N + 2
N + 3
N + 4
N + 5
t
A
t
CH
t
PD
t
SKEW
t
DCO
t
CLK
09996-002
Figure 2. Even/Odd LVDS Mode Data Output Timing