Datasheet

AD9634
Rev. 0 | Page 21 of 32
AD8375
AD9634
1µH
1µH
1nF
1nF
VPOS
VCM
15pF
68nH
2.5kΩ║2pF
301Ω
165Ω
165Ω
5.1pF 3.9pF
180nH1000p
F
1000pF
180nH
220nH
220nH
NOTES
1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS
WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).
2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz.
09996-047
Figure 50. Differential Input Configuration Using the AD8375
An alternative to using a transformer-coupled input at
frequencies in the second Nyquist zone is to use an amplifier
with variable gain. The AD8375 digital variable gain amplifier
(DVGA) provides good performance for driving the AD9634.
Figure 50 shows an example of the AD8375 driving the AD9634
through a band-pass antialiasing filter.
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9634.
The full-scale input range can be adjusted by varying the reference
voltage via SPI. The input span of the ADC tracks reference
voltage changes linearly.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9634 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins by
means of a transformer or a passive component configuration.
These pins are biased internally (see Figure 51) and require no
external bias. If the inputs are floated, the CLK− pin is pulled low
to prevent spurious clocking.
A
V
DD
CLK+
4pF4pF
CLK–
0.9V
09996-048
Figure 51. Equivalent Clock Input Circuit
Clock Input Options
The AD9634 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless
of the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section.
Figure 52 and Figure 53 show two preferable methods for clocking
the AD9634 (at clock rates of up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using an RF balun or RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is
recommended for clock frequencies from 10 MHz to 200 MHz.
The back-to-back Schottky diodes across the secondary windings
of the transformer limit clock excursions into the AD9634 to
approximately 0.8 V p-p differential. This limit helps prevent the
large voltage swings of the clock from feeding through to other
portions of the AD9634, while preserving the fast rise and fall times
of the signal, which are critical for low jitter performance.
390pF
390pF390pF
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50Ω
100Ω
CLK–
CLK+
ADC
Mini-Circuits
®
ADT1-1WT, 1:1Z
XFMR
09996-056
Figure 52. Transformer Coupled Differential Clock (Up to 200 MHz)
390pF 390pF
390pF
CLOCK
INPUT
1nF
25Ω
25Ω
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
09996-057
Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input pins
as shown in Figure 54. The AD9510, AD9511,AD9512, AD9513,
AD9514, AD9515, AD9516, AD9517, AD9518, AD9520, AD9522,
AD9523, AD9524, ADCLK905, ADCLK907, and ADCLK925
clock drivers offer excellent jitter performance.
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
240Ω240Ω
PECL DRIVER
50kΩ 50kΩ
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD95xx,
ADCLKxxx
ADC
09996-051
Figure 54. Differential PECL Sample Clock (Up to 625 MHz)