Datasheet

REV. C–16–
AD9631/AD9632
Layout Considerations
The specified high speed performance of the AD9631 and AD9632
requires careful attention to board layout and component
selection. Proper RF design techniques and low-pass parasitic
component selection are mandatory.
The PCB should have a ground plane covering all unused portions
of the component side of the board to provide a low impedance
path. The ground plane should be removed from the area near
the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see
Figure 10). One end should be connected to the ground plane,
and the other within 1/8 inch of each power pin. An additional
large (0.47 mF–10 mF) tantalum electrolytic capacitor should be
connected in parallel, though not necessarily so close, to supply
current for fast, large signal changes at the output.
The feedback resistor should be located close to the inverting input
pin in order to keep the stray capacitance at this node to a mini-
mum. Capacitance variations of less than 1 pF at the inverting
input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50 W or 75 W and be properly termi-
nated at each end.