Datasheet

AD9628
Rev. 0 | Page 5 of 44
AD9628-105 AD9628-125
Parameter Temp Min Typ Max Min Typ Max Unit
POWER CONSUMPTION
DC Input Full 129 148 mW
Sine Wave Input (DRVDD = 1.8 V CMOS
Output Mode)
1
Full 173 182 201 212 mW
Sine Wave Input (DRVDD = 1.8 V LVDS
Output Mode)
1
Full 243 269 mW
Standby Power
3
Full 108 120 mW
Power-Down Power Full 2.0 2.0 mW
1
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
2
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3
Standby power is measured with a dc input and with the CLK± pins active (1.8 V CMOS mode).
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless
otherwise noted.
Table 2.
AD9628-105 AD9628-125
Parameter
1
Temp Min Typ Max Min Typ Max Unit
SIGNAL-TO-NOISE-RATIO (SNR)
f
IN
= 9.7 MHz 25°C 71.6 71.5 dBFS
f
IN
= 30.5 MHz 25°C 71.6 71.4 dBFS
f
IN
= 70 MHz 25°C 71.3 71.2 dBFS
Full 70.6 70.2 dBFS
f
IN
= 100 MHz
25°C 71.0 70.9 dBFS
f
IN
= 200 MHz 25°C 69.4 69.6 dBFS
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
f
IN
= 9.7 MHz 25°C 71.5 71.4 dBFS
f
IN
= 30.5 MHz 25°C 71.5 71.3 dBFS
f
IN
= 70 MHz 25°C 71.2 71.1 dBFS
Full 70.5 70 dBFS
f
IN
= 100 MHz 25°C 69.9 69.8 dBFS
f
IN
= 200 MHz 25°C
68.1
68.3
dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 9.7 MHz
25°C 11.6 11.6 Bits
f
IN
= 30.5 MHz
25°C
11.6
11.6
Bits
f
IN
= 70 MHz
25°C 11.6 11.5 Bits
f
IN
= 100 MHz
25°C 11.5 11.3 Bits
f
IN
= 200 MHz
25°C 11.0 11.1 Bits
WORST SECOND OR THIRD HARMONIC
f
IN
= 9.7 MHz
25°C
−92 −92
dBc
f
IN
= 30.5 MHz
25°C
−90 −90
dBc
f
IN
= 70 MHz
25°C
−90 −93
dBc
Full
−82 −85
dBc
f
IN
= 100 MHz
25°C
−89 −90
dBc
f
IN
= 200 MHz
25°C
−83 −84
dBc