Datasheet
AD9628
Rev. 0 | Page 17 of 44
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
B D7–/D6–
B D7+/D6+
DRVDD
B D9–/D8–
B D9+/D8+
B D11–/D10– (MSB)
B D11+/D10+ (MSB)
DCO–
DCO+
NC
NC
DRVDD
A D1–/D0– (LSB)
A D1+/D0+ (LSB)
A D3–/D2–
A D3+/D2+
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD
AVDD
VIN+B
VIN–B
AVDD
AVDD
RBIAS
VCM
SENSE
VREF
AVDD
AVDD
VIN–A
VIN+A
AVDD
AVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK+
CLK–
SYNC
NC
NC
NC
NC
NC
NC
DRVDD
B D1–/D0– (LSB)
B D1+/D0+ (LSB)
B D3–/D2–
B D3+/D2+
B D5–/D4–
B D5+/D4+
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
OR+
OR–
A D11+/D10+ (MSB)
A D11–/D10– (MSB)
A D9+/D8+
A D9–/D8–
DRVDD
A D7+/D6+
A D7–/D6–
A D5+/D4+
A D5–/D4–
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9628
CHANNEL MULTIPLEXED LVDS
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
09976-008
Figure 8. LFCSP Channel Multiplexed LVDS Pin Configuration (Top View)
Table 10 Pin Function Descriptions (Channel Multiplexed Parallel LVDS Mode)
Pin No. Mnemonic Type Description
ADC Power Supplies
10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal).
49, 50, 53,
54, 59, 60,
63, 64
AVDD Supply Analog Power Supply (1.8 V Nominal).
4, 5, 6, 7, 8, 9,
26, 27
NC Do Not Connect.
0 AGND, Exposed Pad Ground The exposed thermal pad on the bottom of the package provides the
analog ground for the part. This exposed pad must be connected to ground
for proper operation.
ADC Analog
51 VIN+A Input Differential Analog Input Pin (+) for Channel A.
52 VIN−A Input Differential Analog Input Pin (−) for Channel A.
62 VIN+B Input Differential Analog Input Pin (+) for Channel B.
61 VIN−B Input Differential Analog Input Pin (−) for Channel B.
55 VREF Input/Output Voltage Reference Input/Output.
56 SENSE Input Reference Mode Selection.
58 RBIAS Input/Output External Reference Bias Resistor.
57 VCM Output Common-Mode Level Bias Output for Analog Inputs.
1 CLK+ Input ADC Clock Input—True.
2 CLK− Input ADC Clock Input—Complement.
3 SYNC Input Digital Synchronization Pin. Slave mode only.