Datasheet

AD9613 Data Sheet
Rev. C | Page 32 of 36
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 14 are not currently supported for this device.
Table 14. Memory Map Registers
Addr
(Hex)
Register
Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
Chip Configuration Registers
0x00 SPI port
configuration
(global)
1
0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles
are mirrored
so that LSB-
first mode
or MSB-first
mode
registers
correctly,
regardless
of shift
mode
0x01 Chip ID
(global)
8-bit chip ID[7:0] (AD9613 = 0x83)
(default)
0x83 Read only
0x02 Chip grade
(global)
Open Open Speed grade ID
00 = 250 MSPS
01 = 210 MSPS
11 = 170 MSPS
Open Open Open Open Speed
grade ID
used to
differentiate
devices;
read only
Channel Index and Transfer Registers
0x05 Channel index
(global)
Open Open Open Open Open Open ADC B
(default)
ADC A
(default)
0x03 Bits are set
to
determine
which
device on
the chip
receives the
next write
command;
applies to
local
registers
only
0xFF
Transfer
(global)
Open
Open
Open
Open
Open
Open
Open
Transfer
0x00
Synchron-
ously
transfers
data from
the master
shift register
to the slave
ADC Functions
0x08 Power modes
(local)
Open Open External
power-
down pin
function
(local)
0 = power-
down
1 = standby
Open Open Open Internal power-down mode
(local)
00 = normal operation
01 = full power-down
10 = standby
11 = reserved
0x00 Determines
various
generic
modes of
chip
operation
0x09 Global clock
(global)
Open Open Open Open Open Open Open Duty cycle
stabilizer
(default)
0x01
0x0B Clock divide
(global)
Open Open Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x00 Clock divide
values other
than 000
auto-
matically
cause the
duty cycle
stabilizer to
become
active