Datasheet

AD9601
Rev. 0 | Page 9 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1DA4
2DA5
3DA6
4DA7
5DA8
6(MSB) DA9
7DRVDD
8DRGND
9OVRA
10NIC
11NIC
12(LSB) DB0
13DB1
14DB2
35 VIN+
36 VIN–
37 AVDD
38 AVDD
39 AVDD
40 CML
41 AVDD
42 AVDD
34 AVDD
33 AVDD
32 AVDD
31 RBIAS
30 AVDD
29 PWDN
15
DB3
16
DB4
17
DB5
19
DB7
21
(MSB) DB9
20
DB8
22
OVRB
23
D
RGND
24
DRVDD
25
SDIO/DCS
26
SCLK/DFS
27
CSB
28
RES
ET
18
D
B6
45
CLK–
46
AVDD
47
DRVDD
48
DRGND
49
DCO–
50
DCO+
51
NIC
52
NIC
53
DA0 (LSB)
54
D
A1
44
CLK+
43
A
VDD
TOP VIEW
(Not to Scale)
PIN 0 (EXPOSED PADDLE) = AGND
AD9601
55
DA2
56
DA3
07100-002
Figure 4. Pin Configuration
Table 7. Single Data Rate Mode Pin Function Descriptions
Pin No. Mnemonic Description
30, 32, 33, 34, 37, 38, 39,
41, 42, 43, 46
AVDD 1.8 V Analog Supply.
7, 24, 47 DRVDD 1.8 V Digital Output Supply.
0 AGND
1
Analog Ground.
8, 23, 48 DRGND
1
Digital Output Ground.
35 VIN+ Analog Input—True.
36 VIN− Analog Input—Complement.
40 CML
Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
44 CLK+ Clock Input—True.
45 CLK− Clock Input—Complement.
31 RBIAS
Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.)
Nominally 0.5 V.
28 RESET CMOS-Compatible Chip Reset (Active Low).
25 SDIO/DCS
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer
Select (External Pin Mode).
26 SCLK/DFS Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
27 CSB Serial Port Chip Select (Active Low).
29 PWDN Chip Power-Down.
49 DCO− Data Clock Output—Complement.
50 DCO+ Data Clock Output—True.
53 DA0 (LSB) Output Port A Output Bit 0 (LSB).
54 DA1 Output Port A Output Bit 1.
55 DA2 Output Port A Output Bit 2.
56 DA3 Output Port A Output Bit 3.
1 DA4 Output Port A Output Bit 4.
2 DA5 Output Port A Output Bit 5.
3 DA6 Output Port A Output Bit 6.