Datasheet

AD9601
Rev. 0 | Page 17 of 32
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9601 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ pin and the
CLK− pin via a transformer or capacitors. These pins are biased
internally and require no additional bias.
Figure 36 shows one preferred method for clocking the AD9601.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9601 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9601 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
0.1µF
0.1µF
0.1µF0.1µF
CLOCK
INPUT
50Ω
100Ω
CLK–
CLK+
ADC
AD9601
MINI-CIRCUITS
ADT1–1WT, 1:1Z
XFMR
SCHOTTKY
DIODES:
HSM2812
07100-011
Figure 36. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac couple a
differential PECL signal to the sample clock input pins, as
shown in
Figure 37. The AD9510/AD9511/AD9512/AD9513/
AD9514/AD9515 family of clock drivers offers excellent jitter
performance.
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
240Ω240Ω
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
50Ω* 50Ω*
CLK
CLK
*50Ω RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9601
PECL DRIVER
CLOCK
INPUT
CLOCK
INPUT
07100-012
Figure 37. Differential PECL Sample Clock
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
50Ω* 50Ω*
CLK
CLK
*50Ω RESISTORS ARE OPTIONAL.
CLK–
CLK+
ADC
AD9601
LVDS DRIVER
CLOCK
INPUT
CLOCK
INPUT
07100-013
Figure 38. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see
Figure 39). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V, making the
selection of the drive logic voltage very flexible.
0.1µF
0.1µF
0.1µF
39kΩ
CMOS DRIVER
50Ω*
OPTIONAL
100Ω
0.1µF
CLK
CLK
*50Ω RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9601
A
D9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLOCK
INPUT
07100-014
Figure 39. Single-Ended 1.8 V CMOS Sample Clock
0.1µF
0.1µF
0.1µF
CMOS DRIVER
CLK
CLK
*50Ω RESISTOR IS OPTIONAL.
0.1µF
CLK–
CLK+
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
ADC
AD9601
CLOCK
INPUT
50Ω*
OPTIONAL
100Ω
07100-015
Figure 40. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance
is required on the clock duty cycle to maintain dynamic per-
formance characteristics. The AD9601 contains a duty cycle
stabilizer (DCS) that retimes the nonsampling edge, providing
an internal clock signal with a nominal 50% duty cycle. This
allows a wide range of clock input duty cycles without affecting
the performance of the AD9601. When the DCS is on, noise
and distortion performance are nearly flat for a wide range of
duty cycles. However, some applications may require the DCS
function to be off. If so, keep in mind that the dynamic range
performance can be affected when operated in this mode. See the
AD9601 Configuration Using the SPI section for more details
on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.